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authorNate Begeman <natebegeman@mac.com>2005-10-08 01:21:27 +0000
committerNate Begeman <natebegeman@mac.com>2005-10-08 01:21:27 +0000
commit02f77d1e8357c0abe3fc51b421cb6c0be006f3a0 (patch)
tree7dbefd0ba7b5a99f4acd9134e2f83adf674c4186
parentf845b4563a960047b1092618093a79dc0bf998a8 (diff)
Remove a file that is no longer used
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23666 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPC64RegisterInfo.td46
1 files changed, 0 insertions, 46 deletions
diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.td b/lib/Target/PowerPC/PPC64RegisterInfo.td
deleted file mode 100644
index 4555b45d4b..0000000000
--- a/lib/Target/PowerPC/PPC64RegisterInfo.td
+++ /dev/null
@@ -1,46 +0,0 @@
-//===- PPC64RegisterInfo.td - The PowerPC64 Register File --*- tablegen -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-include "PowerPCRegisterInfo.td"
-
-/// Register classes
-// Allocate volatiles first
-// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
-def GPRC : RegisterClass<"PPC64", i64, 64,
- [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
- R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
- R16, R15, R14, R13, R31, R0, R1, LR]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(MachineFunction &MF) const;
- iterator allocation_order_end(MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- GPRCClass::iterator
- GPRCClass::allocation_order_begin(MachineFunction &MF) const {
- return begin() + ((TargetAIX == PPCTarget) ? 1 : 0);
- }
- GPRCClass::iterator
- GPRCClass::allocation_order_end(MachineFunction &MF) const {
- if (hasFP(MF))
- return end()-4;
- else
- return end()-3;
- }
- }];
-}
-
-def FPRC : RegisterClass<"PPC64", f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
- F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
- F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
-
-def CRRC : RegisterClass<"PPC64", i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;