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authorChris Lattner <sabre@nondot.org>2006-03-27 03:28:57 +0000
committerChris Lattner <sabre@nondot.org>2006-03-27 03:28:57 +0000
commiteeaf72af39afce402236f71702d878ce65491b6a (patch)
tree072dfa3a68f811ddae40373497f677212288baa2
parenta8299deab75b9675f46a2ba03ea8a1ba19ffe280 (diff)
Fix the JIT encoding of VSPLTI*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27159 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPCInstrAltivec.td18
-rw-r--r--lib/Target/PowerPC/PPCInstrFormats.td15
2 files changed, 24 insertions, 9 deletions
diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td
index 8acce42d4c..360f7db3e5 100644
--- a/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -290,15 +290,15 @@ def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
VSPLT_shuffle_mask:$UIMM))]>;
-def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
- "vspltisb $vD, $SIMM", VecPerm,
- [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
-def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
- "vspltish $vD, $SIMM", VecPerm,
- [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
-def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
- "vspltisw $vD, $SIMM", VecPerm,
- [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
+def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
+ "vspltisb $vD, $SIMM", VecPerm,
+ [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
+def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
+ "vspltish $vD, $SIMM", VecPerm,
+ [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
+def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
+ "vspltisw $vD, $SIMM", VecPerm,
+ [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
// Altivec Comparisons.
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 7319463a73..9f87b278e6 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -663,6 +663,21 @@ class VXForm_2<bits<11> xo, dag OL, string asmstr,
let Inst{21-31} = xo;
}
+class VXForm_3<bits<11> xo, dag OL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OL, asmstr, itin> {
+ bits<5> VD;
+ bits<5> IMM;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = VD;
+ let Inst{11-15} = IMM;
+ let Inst{16-20} = 0;
+ let Inst{21-31} = xo;
+}
+
+
// E-4 VXR-Form
class VXRForm_1<bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>