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| author | Evan Cheng <evan.cheng@apple.com> | 2009-08-12 02:03:03 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-08-12 02:03:03 +0000 |
| commit | c972165b114477a57f0c6e0984b1be81d5ccdd82 (patch) | |
| tree | d64eaf3a43599655947a216424647b015e155555 | |
| parent | ea253b99e907a4171d49547fc5d99c837af5d0b9 (diff) | |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78778 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 44dcdac537..4b4a2ec02b 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -614,17 +614,17 @@ def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU, // FIXME: Add actual movcc in IT blocks for Thumb2. let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler. def tMOVCCr : - PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), IIC_iALU, - "@ tMOVCCr $cc", - [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; + PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), + NoItinerary, "@ tMOVCCr $cc", + [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; // tLEApcrel - Load a pc-relative address into a register without offending the // assembler. def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU, "adr $dst, #$label", []>; -def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, lane_cst:$id), IIC_iALU, - "adr $dst, #${label}_${id}", []>; +def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, lane_cst:$id), + IIC_iALU, "adr $dst, #${label}_${id}", []>; //===----------------------------------------------------------------------===// // TLS Instructions |