diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2009-11-20 02:10:27 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-11-20 02:10:27 +0000 |
| commit | 9b82425cb0105fd5704f6b9bcd5e7693b05b1759 (patch) | |
| tree | 71ae23f126389c602b32c462d679511367f95c9c | |
| parent | 2e7e94826a4cf6715b4c07d779fb84994c0bc47b (diff) | |
Also CSE non-pic load from constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89440 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/Thumb2/machine-licm.ll | 13 |
2 files changed, 15 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index b50b6098dd..33a96f67d6 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -978,7 +978,10 @@ bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const { int Opcode = MI0->getOpcode(); - if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) { + if (Opcode == ARM::t2LDRpci || + Opcode == ARM::t2LDRpci_pic || + Opcode == ARM::tLDRpci || + Opcode == ARM::tLDRpci_pic) { if (MI1->getOpcode() != Opcode) return false; if (MI0->getNumOperands() != MI1->getNumOperands()) diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 912939bf24..88e21551be 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC ; rdar://7353541 ; rdar://7354376 @@ -17,12 +18,20 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 ; CHECK: ldr.n r2, LCPI1_0 -; CHECK: add r2, pc ; CHECK: ldr r{{[0-9]+}}, [r2] ; CHECK: LBB1_2 ; CHECK: LCPI1_0: ; CHECK-NOT: LCPI1_1: ; CHECK: .section + +; PIC: BB#1 +; PIC: ldr.n r2, LCPI1_0 +; PIC: add r2, pc +; PIC: ldr r{{[0-9]+}}, [r2] +; PIC: LBB1_2 +; PIC: LCPI1_0: +; PIC-NOT: LCPI1_1: +; PIC: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb |