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| author | Tanya Lattner <tonic@nondot.org> | 2010-11-18 22:06:46 +0000 |
|---|---|---|
| committer | Tanya Lattner <tonic@nondot.org> | 2010-11-18 22:06:46 +0000 |
| commit | 9684a7c1281e7d7f6d7ab7c3f8484fe2138f39bc (patch) | |
| tree | fd5dc7cde824c4363af7e186df2ff3602bafe0f9 | |
| parent | 24d22d27640e9de954a5ac26f51a45cc96bb9135 (diff) | |
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll | 8 |
2 files changed, 10 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 299009b6bd..7e3f98acd9 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4985,7 +4985,8 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, EVT VT = N->getValueType(0); // Nothing to be done for scalar shifts. - if (! VT.isVector()) + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (!VT.isVector() || !TLI.isTypeLegal(VT)) return SDValue(); assert(ST->hasNEON() && "unexpected vector shift"); diff --git a/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll b/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll new file mode 100644 index 0000000000..b9cf352023 --- /dev/null +++ b/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -march=arm -mattr=+neon +define void @lshrIllegalType(<8 x i32>* %A) nounwind { + %tmp1 = load <8 x i32>* %A + %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> + store <8 x i32> %tmp2, <8 x i32>* %A + ret void +} + |