diff options
| author | Dan Gohman <gohman@apple.com> | 2008-08-13 19:47:40 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-13 19:47:40 +0000 |
| commit | 925a7e8ed6522f291b4ae559ccfa56db461016e3 (patch) | |
| tree | 523559c053e05f9fc95ddbd37acbf18efe091da4 | |
| parent | 20ab78b8b0d6740d94783aab02055f8aed3ed666 (diff) | |
Rename SelectionDAGISel's FastISel to Fast, to begin to make
room for the new FastISel instruction selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54749 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGISel.h | 4 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 804ccf3e59..7471039477 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -42,12 +42,12 @@ public: MachineBasicBlock *BB; AliasAnalysis *AA; CollectorMetadata *GCI; - bool FastISel; + bool Fast; std::vector<SDNode*> TopOrder; static char ID; explicit SelectionDAGISel(TargetLowering &tli, bool fast = false) : - FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), FastISel(fast), DAGSize(0) {} + FunctionPass((intptr_t)&ID), TLI(tli), GCI(0), Fast(fast), DAGSize(0) {} TargetLowering &getTargetLowering() { return TLI; } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index d1c49d00ee..815fdb7cc7 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -5379,7 +5379,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) { if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName); - if (!FastISel && EnableValueProp) + if (!Fast && EnableValueProp) ComputeLiveOutVRegInfo(DAG); // Third, instruction select all of the operations to machine code, adding the @@ -5448,7 +5448,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF, BasicBlock *LLVMBB = &*I; PHINodesToUpdate.clear(); - if (!FastISel || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB])) + if (!Fast || !SISel.SelectBasicBlock(LLVMBB, FuncInfo.MBBMap[LLVMBB])) SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator); FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator); } @@ -5696,7 +5696,7 @@ ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) { RegisterScheduler::setDefault(Ctor); } - ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, FastISel); + ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast); Scheduler->Run(); return Scheduler; |