diff options
| author | Bill Wendling <isanbard@gmail.com> | 2011-10-15 00:27:44 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2011-10-15 00:27:44 +0000 |
| commit | 918f2155e90613bcf222ac5499f845d231bdfd57 (patch) | |
| tree | 13b580a1c654a2fcd72c3e37a9e7ef7b00ccb173 | |
| parent | 46995fa7e2eead5759d13ddc64ef073c1d527f12 (diff) | |
Mark registers as DEAD because they're really just clobbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142027 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 6ead63f5ca..8e065ee194 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5932,7 +5932,7 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { for (unsigned i = 0; SavedRegs[i] != 0; ++i) { if (!TRC->contains(SavedRegs[i])) continue; if (!DefRegs[SavedRegs[i]]) - MIB.addReg(SavedRegs[i], RegState::Implicit | RegState::Define); + MIB.addReg(SavedRegs[i], RegState::ImplicitDefine | RegState::Dead); } break; |