diff options
| author | Manman Ren <mren@apple.com> | 2012-06-07 00:42:47 +0000 |
|---|---|---|
| committer | Manman Ren <mren@apple.com> | 2012-06-07 00:42:47 +0000 |
| commit | 87253c2ebdae320ee24a2cbf10f8de9b3acba763 (patch) | |
| tree | 4fde1630bccf2ca0978b056e2d827f687d9ee51b | |
| parent | d66ec52b62a61da2a5d65b8fe524bbffb3d541ef (diff) | |
X86: replace SUB with CMP if possible
This patch will optimize the following
movq %rdi, %rax
subq %rsi, %rax
cmovsq %rsi, %rdi
movq %rdi, %rax
to
cmpq %rsi, %rdi
cmovsq %rsi, %rdi
movq %rdi, %rax
Perform this optimization if the actual result of SUB is not used.
rdar: 11540023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158126 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 15 | ||||
| -rw-r--r-- | test/CodeGen/X86/jump_sign.ll | 11 |
2 files changed, 25 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 4baa1a6bbb..57f61ab38f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8271,7 +8271,13 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, // Otherwise use a regular EFLAGS-setting instruction. switch (Op.getNode()->getOpcode()) { default: llvm_unreachable("unexpected operator!"); - case ISD::SUB: Opcode = X86ISD::SUB; break; + case ISD::SUB: + // If the only use of SUB is EFLAGS, use CMP instead. + if (Op.hasOneUse()) + Opcode = X86ISD::CMP; + else + Opcode = X86ISD::SUB; + break; case ISD::OR: Opcode = X86ISD::OR; break; case ISD::XOR: Opcode = X86ISD::XOR; break; case ISD::AND: Opcode = X86ISD::AND; break; @@ -8297,6 +8303,13 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, DAG.getConstant(0, Op.getValueType())); + if (Opcode == X86ISD::CMP) { + SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0), + Op.getOperand(1)); + DAG.ReplaceAllUsesWith(Op, New); + return SDValue(New.getNode(), 0); + } + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); SmallVector<SDValue, 4> Ops; for (unsigned i = 0; i != NumOperands; ++i) diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll index 94cbe5d193..d253e15774 100644 --- a/test/CodeGen/X86/jump_sign.ll +++ b/test/CodeGen/X86/jump_sign.ll @@ -83,3 +83,14 @@ entry: %cond = select i1 %cmp, i32 %sub, i32 0 ret i32 %cond } +; rdar://11540023 +define i32 @n(i32 %x, i32 %y) nounwind { +entry: +; CHECK: n: +; CHECK-NOT: sub +; CHECK: cmp + %sub = sub nsw i32 %x, %y + %cmp = icmp slt i32 %sub, 0 + %y.x = select i1 %cmp, i32 %y, i32 %x + ret i32 %y.x +} |