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authorEvan Cheng <evan.cheng@apple.com>2009-01-05 08:45:01 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-01-05 08:45:01 +0000
commit7877112775b97d13e225124d6f1181c30d75853a (patch)
tree4bfe94c6a230eb0c600eaacc54020c593eddcebc
parentd0f9c730d4f0dcf008da0814ebcd6da90e4ba995 (diff)
Atom and Core i7 do not have same model number after all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61686 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86Subtarget.cpp7
1 files changed, 3 insertions, 4 deletions
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index c6cda56f7d..608f352ddf 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -204,7 +204,6 @@ static const char *GetCurrentX86CPU() {
unsigned Family = 0;
unsigned Model = 0;
DetectFamilyModel(EAX, Family, Model);
- bool HasSSE42 = (ECX >> 19) & 0x1;
X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;
@@ -252,10 +251,10 @@ static const char *GetCurrentX86CPU() {
case 4:
case 6: // same as 4, but 65nm
return (Em64T) ? "nocona" : "prescott";
+ case 26:
+ return "corei7";
case 28:
- // Intel Atom, and Core i7 both have this model.
- // Atom has SSSE3, Core i7 has SSE4.2
- return (HasSSE42) ? "corei7" : "atom";
+ return "atom";
default:
return (Em64T) ? "x86-64" : "pentium4";
}