diff options
| author | Chris Lattner <sabre@nondot.org> | 2003-08-07 04:49:16 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2003-08-07 04:49:16 +0000 |
| commit | 69666e552ef0f4d9437de8b323de80255bf035a1 (patch) | |
| tree | fb6b4389e2db0315d9edb5e6d1c6ca58fb301e8c | |
| parent | edea6d646b1149d121d897c7599bd5daf5590f02 (diff) | |
This register is never used, disable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7661 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index e08b0892be..85dbcadec4 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -45,7 +45,7 @@ let Namespace = "X86" in { // This is a slimy hack to make it possible to say that flags are clobbered... // Ideally we'd model instructions based on which particular flag(s) they // could clobber. - def EFLAGS : Register; + //def EFLAGS : Register; } //===----------------------------------------------------------------------===// @@ -96,5 +96,5 @@ def RFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; // Registers which cannot be allocated... and are thus left unnamed. def : RegisterClass<f80, 4, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>; -def : RegisterClass<i16, 2, [EFLAGS]>; +//def : RegisterClass<i16, 2, [EFLAGS]>; |