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authorOwen Anderson <resistor@mac.com>2010-11-01 21:08:20 +0000
committerOwen Anderson <resistor@mac.com>2010-11-01 21:08:20 +0000
commit648b20d5dbc54391f0d38c6ff16cf304bf3cb297 (patch)
treeb24a5a8786d39d2ce346f466553bf4082f1dc6dd
parent99f535242c71d795c11bf54aa6d30ddbed465e9a (diff)
When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low
bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117953 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Transforms/InstCombine/InstCombineShifts.cpp2
-rw-r--r--test/Transforms/InstCombine/2010-11-01-lshr-mask.ll20
2 files changed, 21 insertions, 1 deletions
diff --git a/lib/Transforms/InstCombine/InstCombineShifts.cpp b/lib/Transforms/InstCombine/InstCombineShifts.cpp
index 27716b886a..012d238729 100644
--- a/lib/Transforms/InstCombine/InstCombineShifts.cpp
+++ b/lib/Transforms/InstCombine/InstCombineShifts.cpp
@@ -157,7 +157,7 @@ static bool CanEvaluateShifted(Value *V, unsigned NumBits, bool isLeftShift,
if (CI->getZExtValue() > NumBits) {
unsigned LowBits = CI->getZExtValue() - NumBits;
if (MaskedValueIsZero(I->getOperand(0),
- APInt::getLowBitsSet(TypeWidth, LowBits)))
+ APInt::getLowBitsSet(TypeWidth, LowBits) << NumBits))
return true;
}
diff --git a/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll b/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
new file mode 100644
index 0000000000..d74c70e4f7
--- /dev/null
+++ b/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
@@ -0,0 +1,20 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+; <rdar://problem/8606771>
+
+define i32 @main(i32 %argc) nounwind ssp {
+entry:
+ %tmp3151 = trunc i32 %argc to i8
+ %tmp3161 = or i8 %tmp3151, -17
+ %tmp3162 = and i8 %tmp3151, 122
+ %tmp3163 = xor i8 %tmp3162, -17
+ %tmp4114 = shl i8 %tmp3163, 6
+ %tmp4115 = xor i8 %tmp4114, %tmp3163
+ %tmp4120 = xor i8 %tmp3161, %tmp4115
+; CHECK: lshr i8 %tmp4115, 1
+; CHECK-NOT: shl i8 %tmp4126, 6
+ %tmp4126 = lshr i8 %tmp4120, 7
+ %tmp4127 = mul i8 %tmp4126, 64
+ %tmp4086 = zext i8 %tmp4127 to i32
+; CHECK: ret i32
+ ret i32 %tmp4086
+}