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| author | Bill Wendling <isanbard@gmail.com> | 2011-10-14 23:55:44 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2011-10-14 23:55:44 +0000 |
| commit | 5d79859f66fa1540d5a1c1e9e4f4e080e6e956f1 (patch) | |
| tree | 4e8f3e94e55f661797ccd5c0eceec62ce514fed5 | |
| parent | 969c9ef0dd271905136f21a6c51dd0839ef01cce (diff) | |
Make sure that the register is in the register class before adding it as a machine op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142021 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f3bc719450..f1000de429 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5921,9 +5921,11 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { MachineInstrBuilder MIB(&*II); - for (unsigned i = 0; SavedRegs[i] != 0; ++i) + for (unsigned i = 0; SavedRegs[i] != 0; ++i) { + if (!TRC->contains(SavedRegs[i])) continue; if (!DefRegs[SavedRegs[i]]) MIB.addReg(SavedRegs[i], RegState::Implicit | RegState::Define); + } break; } |