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| author | Bob Wilson <bob.wilson@apple.com> | 2010-12-18 00:04:33 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-12-18 00:04:33 +0000 |
| commit | 3deb45149a2eaecfc9453db2a7e840531b930cc6 (patch) | |
| tree | 71b3745649d3fa8e03f1cb69e0ac34a9230250c3 | |
| parent | 3a75b9bc8fed6c7f3f30470d3f3e28ac83df9d40 (diff) | |
Fix result type of Neon floating-point comparisons against zero.
The result vector elements are always integers. Radar 8782191.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122112 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vcge.ll | 19 |
2 files changed, 21 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index e27a4a8911..b6d25aa98c 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -2372,7 +2372,7 @@ multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4, (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, opc, "f32", asm, "", - [(set DPR:$Vd, (v2f32 (OpNode (v2f32 DPR:$Vm))))]> { + [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> { let Inst{10} = 1; // overwrite F = 1 } @@ -2392,7 +2392,7 @@ multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4, (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, opc, "f32", asm, "", - [(set QPR:$Vd, (v4f32 (OpNode (v4f32 QPR:$Vm))))]> { + [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> { let Inst{10} = 1; // overwrite F = 1 } } diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll index f190931f1b..bf5f0b9efb 100644 --- a/test/CodeGen/ARM/vcge.ll +++ b/test/CodeGen/ARM/vcge.ll @@ -182,3 +182,22 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind { %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 } + +; Radar 8782191 +; Floating-point comparisons against zero produce results with integer +; elements, not floating-point elements. +define void @test_vclez_fp() nounwind optsize { +;CHECK: test_vclez_fp +;CHECK: vcle.f32 +entry: + %0 = fcmp ole <4 x float> undef, zeroinitializer + %1 = sext <4 x i1> %0 to <4 x i16> + %2 = add <4 x i16> %1, zeroinitializer + %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %4 = add <8 x i16> %3, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %5 = trunc <8 x i16> %4 to <8 x i8> + tail call void @llvm.arm.neon.vst1.v8i8(i8* undef, <8 x i8> %5, i32 1) + unreachable +} + +declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind |