diff options
author | Chris Lattner <sabre@nondot.org> | 2006-01-25 08:00:36 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2006-01-25 08:00:36 +0000 |
commit | 31e63881b373311ad699ba70aec6b69258773406 (patch) | |
tree | 3dd0b63322fed65d2e99df40ceaba5bbf9d5bb5d | |
parent | fb709b6817426c99d2ce48a2d08ef20e376a0e06 (diff) |
Loosen up these checks to allow direct uses of ESP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25595 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelPattern.cpp | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index 2a2ebd9773..46b0e8dc18 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -2903,13 +2903,21 @@ static SDOperand GetAdjustedArgumentStores(SDOperand Chain, int Offset, if (OrigDest.getOpcode() == ISD::CopyFromReg) { OrigOffset = 0; assert(cast<RegisterSDNode>(OrigDest.getOperand(1))->getReg() == X86::ESP); - } else { + } else if (OrigDest.getOpcode() == ISD::ADD && + isa<ConstantSDNode>(OrigDest.getOperand(1)) && + OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg && + cast<RegisterSDNode>(OrigDest.getOperand(0).getOperand(1))->getReg() + == X86::ESP) { + // We expect only (ESP+C) + OrigOffset = cast<ConstantSDNode>(OrigDest.getOperand(1))->getValue(); + } else if (OrigDest.getOpcode() == ISD::Register) { // We expect only (ESP+C) + OrigOffset = 0; + } else { assert(OrigDest.getOpcode() == ISD::ADD && isa<ConstantSDNode>(OrigDest.getOperand(1)) && - OrigDest.getOperand(0).getOpcode() == ISD::CopyFromReg && - cast<RegisterSDNode>(OrigDest.getOperand(0).getOperand(1))->getReg() - == X86::ESP); + OrigDest.getOperand(0).getOpcode() == ISD::Register && + cast<RegisterSDNode>(OrigDest.getOperand(0))->getReg() == X86::ESP); OrigOffset = cast<ConstantSDNode>(OrigDest.getOperand(1))->getValue(); } |