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| author | Evan Cheng <evan.cheng@apple.com> | 2010-09-25 01:06:02 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-25 01:06:02 +0000 |
| commit | 27fdcd1c95fb1ded32d5e3876fed3c0f0641ab30 (patch) | |
| tree | f21ba449a1c45c2a03a5cd197b4e291d4b91c4dd | |
| parent | c69a00047013a0e2e07ae44c38e013a7d905b10e (diff) | |
Remove a unused instruction itinerary class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114782 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 1 |
4 files changed, 0 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 06a5f30f00..c64c4392a3 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -17,7 +17,6 @@ def IIC_iALUsi : InstrItinClass; def IIC_iALUsr : InstrItinClass; def IIC_iUNAr : InstrItinClass; def IIC_iUNAsi : InstrItinClass; -def IIC_iUNAsr : InstrItinClass; def IIC_iEXTr : InstrItinClass; def IIC_iEXTAr : InstrItinClass; def IIC_iCMPi : InstrItinClass; diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 48d1905aee..864ada0162 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -40,7 +40,6 @@ def CortexA8Itineraries : ProcessorItineraries< // Unary Instructions that produce a result InstrItinData<IIC_iUNAr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, InstrItinData<IIC_iUNAsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1]>, - InstrItinData<IIC_iUNAsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 1, 1]>, // // Zero and sign extension instructions InstrItinData<IIC_iEXTr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>, diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 6d547295ea..4118b90907 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -50,7 +50,6 @@ def CortexA9Itineraries : ProcessorItineraries< // Unary Instructions that produce a result InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 2]>, InstrItinData<IIC_iUNAsi , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 1]>, - InstrItinData<IIC_iUNAsr , [InstrStage<3, [A9_Pipe0, A9_Pipe1]>], [2, 1, 1]>, // // Zero and sign extension instructions InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [2, 1]>, diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index efead92714..866e2e1e23 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -33,7 +33,6 @@ def ARMV6Itineraries : ProcessorItineraries< // Unary Instructions that produce a result InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, InstrItinData<IIC_iUNAsi , [InstrStage<1, [V6_Pipe]>], [2, 1]>, - InstrItinData<IIC_iUNAsr , [InstrStage<2, [V6_Pipe]>], [3, 2, 1]>, // // Zero and sign extension instructions InstrItinData<IIC_iEXTr , [InstrStage<1, [V6_Pipe]>], [1, 1]>, |