Re-fix hiding the Frame Pointer from the register allocator in functions

that have a frame pointer.  This change fixes Burg.  In addition, make
the necessary changes to floating point code gen and constant loading after
Chris Lattner's fixes to the asm writer.  These changes fix MallocBench/gs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15873 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 11 insertions, 23 deletions

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 50fd87b142..d4d658b58e 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -618,13 +618,14 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
     unsigned GlobalBase = makeAnotherReg(Type::IntTy);
     unsigned Reg1 = makeAnotherReg(Type::IntTy);
     unsigned Reg2 = makeAnotherReg(Type::IntTy);
+    unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
     // Move value at base + distance into return reg
     copyGlobalBaseToRegister(MBB, IP, GlobalBase);
     BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1).addReg(GlobalBase)
       .addConstantPoolIndex(CPI);
     BuildMI(*MBB, IP, PPC::LOADLoDirect, 2, Reg2).addReg(Reg1)
       .addConstantPoolIndex(CPI);
-    BuildMI(*MBB, IP, PPC::LFD, 2, R).addSImm(0).addReg(Reg2);
+    BuildMI(*MBB, IP, Opcode, 2, R).addSImm(0).addReg(Reg2);
   } else if (isa<ConstantPointerNull>(C)) {
     // Copy zero (null pointer) to the register.
     BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
@@ -1824,16 +1825,10 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
     const Type *Ty = Op1->getType();
     assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
 
-    unsigned Opcode = OpcodeTab[1][OperatorClass];
-    unsigned Op1Reg = getReg(Op1C, BB, IP);
+    unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass];
     unsigned Op0Reg = getReg(Op0, BB, IP);
-    if (Ty == Type::DoubleTy) {
-      BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
-    } else {
-      unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
-      BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
-      BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
-    }
+    unsigned Op1Reg = getReg(Op1C, BB, IP);
+    BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
     return;
   }
   
@@ -1851,21 +1846,14 @@ void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
       const Type *Ty = Op0C->getType();
       assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
 
-      unsigned Opcode = OpcodeTab[1][OperatorClass];
+      unsigned Opcode = OpcodeTab[Ty == Type::DoubleTy][OperatorClass];
       unsigned Op0Reg = getReg(Op0C, BB, IP);
       unsigned Op1Reg = getReg(Op1, BB, IP);
-      if (Ty == Type::DoubleTy) {
-        BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
-      } else {
-        unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
-        BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addReg(Op1Reg);
-        BuildMI(*BB, IP, PPC::FRSP, 1, DestReg).addReg(TmpReg);
-      }
+      BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
       return;
     }
 
   unsigned Opcode = OpcodeTab[Op0->getType() != Type::FloatTy][OperatorClass];
-  //unsigned Opcode = OpcodeTab[OperatorClass];
   unsigned Op0r = getReg(Op0, BB, IP);
   unsigned Op1r = getReg(Op1, BB, IP);
   BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
diff --git a/lib/Target/PowerPC/PPC32RegisterInfo.td b/lib/Target/PowerPC/PPC32RegisterInfo.td
index 364b1d91d3..2f80c01437 100644
--- a/lib/Target/PowerPC/PPC32RegisterInfo.td
+++ b/lib/Target/PowerPC/PPC32RegisterInfo.td
@@ -17,8 +17,8 @@ include "PowerPCRegisterInfo.td"
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
 def GPRC : RegisterClass<i32, 8,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
-      R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
-      R16, R15, R14, R13, R0, R1, LR]>
+      R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
+      R16, R15, R14, R13, R31, R0, R1, LR]>
 {
   let Methods = [{
     iterator allocation_order_begin(MachineFunction &MF) const {
diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.td b/lib/Target/PowerPC/PPC64RegisterInfo.td
index f39ef1cbff..b922676cc5 100644
--- a/lib/Target/PowerPC/PPC64RegisterInfo.td
+++ b/lib/Target/PowerPC/PPC64RegisterInfo.td
@@ -17,8 +17,8 @@ include "PowerPCRegisterInfo.td"
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
 def GPRC : RegisterClass<i64, 8,
      [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
-      R31, R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
-      R16, R15, R14, R13, R0, R1, LR]>
+      R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
+      R16, R15, R14, R13, R31, R0, R1, LR]>
 {
   let Methods = [{
     iterator allocation_order_begin(MachineFunction &MF) const {