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authorDan Gohman <gohman@apple.com>2008-08-14 22:53:18 +0000
committerDan Gohman <gohman@apple.com>2008-08-14 22:53:18 +0000
commitef521f14b7046a0f7ec169696a13b473c3ab4aee (patch)
tree0f69bc297bf20e89b40ec15d1910512ac05417a3
parent44eb65cf58e3ab9b5621ce72256d1621a18aeed7 (diff)
Also avoid pinsrw and pinsrb with a variable insertelement index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54803 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 6b95034c02..6488a1a832 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4143,7 +4143,8 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
SDValue N1 = Op.getOperand(1);
SDValue N2 = Op.getOperand(2);
- if ((EVT.getSizeInBits() == 8) || (EVT.getSizeInBits() == 16)) {
+ if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
+ isa<ConstantSDNode>(N2)) {
unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
: X86ISD::PINSRW;
// Transform it so it match pinsr{b,w} which expects a GR32 as its second