Remember to promote load/store types for stack to register size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115984 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 0 deletions

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 497259c407..05209aa2f1 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -629,6 +629,9 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
 bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
   Value *Op0 = I->getOperand(0);
 
+  // Promote load/store types.
+  if (VT == MVT::i8 || VT == MVT::i16) VT = MVT::i32;
+
   // Verify it's an alloca.
   if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
     DenseMap<const AllocaInst*, int>::iterator SI =
@@ -735,6 +738,9 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
 bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
   Value *Op1 = I->getOperand(1);
 
+  // Promote load/store types.
+  if (VT == MVT::i8 || VT == MVT::i16) VT = MVT::i32;
+
   // Verify it's an alloca.
   if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
     DenseMap<const AllocaInst*, int>::iterator SI =