diff options
author | Evan Cheng <evan.cheng@apple.com> | 2009-05-06 18:25:01 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-05-06 18:25:01 +0000 |
commit | caab129cd19441817906ea5ca69e341e81c598e3 (patch) | |
tree | 418339ea47b952d55016d44bb9bb4e3b7625bedf | |
parent | ee08da89565714ca143d4754f167e3277974fc19 (diff) |
Do not use register as base ptr of pre- and post- inc/dec load / store nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 | ||||
-rw-r--r-- | test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll | 11 |
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 1378f25387..10b7576a69 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4536,7 +4536,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { // Check #1. Preinc'ing a frame index would require copying the stack pointer // (plus the implicit offset) to a register to preinc anyway. - if (isa<FrameIndexSDNode>(BasePtr)) + if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) return false; // Check #2. @@ -4663,6 +4663,9 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { // nor a successor of N. Otherwise, if Op is folded that would // create a cycle. + if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) + continue; + // Check for #1. bool TryNext = false; for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), diff --git a/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll new file mode 100644 index 0000000000..2bca6e62fc --- /dev/null +++ b/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -mtriple=arm-linuxeabi-unknown-gnu -mattr=+v6 +; PR4166 + + %"byte[]" = type { i32, i8* } + %tango.time.Time.Time = type { i64 } + +define fastcc void @t() { +entry: + %tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0] + ret void +} |