diff options
author | Chris Lattner <sabre@nondot.org> | 2005-04-30 04:25:35 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2005-04-30 04:25:35 +0000 |
commit | c5dcb53bea2b3d735f7e419dd9b1f7fb893d8e47 (patch) | |
tree | 59e6ce4c241fb0964345d68f51b222f382ea77cd | |
parent | 5434b429c8675c12b5be91509d93cc74eb178e56 (diff) |
Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by
Morten Ofstad!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21632 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelPattern.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index d7ea0e3c8e..8b3f31cecf 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -24,6 +24,7 @@ #include "llvm/CodeGen/SSARegMap.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/Support/MathExtras.h" #include "llvm/ADT/Statistic.h" #include <set> @@ -64,6 +65,11 @@ namespace { setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand); setOperationAction(ISD::SREM , MVT::f64 , Expand); + if (!UnsafeFPMath) { + setOperationAction(ISD::FSIN , MVT::f64 , Expand); + setOperationAction(ISD::FCOS , MVT::f64 , Expand); + } + // These should be promoted to a larger select which is supported. /**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote); setOperationAction(ISD::SELECT , MVT::i8 , Promote); @@ -1831,6 +1837,8 @@ unsigned ISel::SelectExpr(SDOperand N) { case ISD::FABS: case ISD::FNEG: + case ISD::FSIN: + case ISD::FCOS: case ISD::FSQRT: assert(N.getValueType()==MVT::f64 && "Illegal type for this operation"); Tmp1 = SelectExpr(Node->getOperand(0)); @@ -1839,6 +1847,8 @@ unsigned ISel::SelectExpr(SDOperand N) { case ISD::FABS: BuildMI(BB, X86::FABS, 1, Result).addReg(Tmp1); break; case ISD::FNEG: BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1); break; case ISD::FSQRT: BuildMI(BB, X86::FSQRT, 1, Result).addReg(Tmp1); break; + case ISD::FSIN: BuildMI(BB, X86::FSIN, 1, Result).addReg(Tmp1); break; + case ISD::FCOS: BuildMI(BB, X86::FCOS, 1, Result).addReg(Tmp1); break; } return Result; |