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| author | Johnny Chen <johnny.chen@apple.com> | 2011-03-24 22:04:39 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-03-24 22:04:39 +0000 |
| commit | c39b6271be255a88fc9481d10894899b0f747ee3 (patch) | |
| tree | 4571f6ef6df50acc64c4ac253d82b260473801ca | |
| parent | 18a41c92c3adc64f5f4f0400d8b462d4b2417378 (diff) | |
Handle the added VBICiv*i* NEON instructions, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 9 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/neon-tests.txt | 3 |
2 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 5930e9e7db..b839a02d6a 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -2302,6 +2302,7 @@ static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn, // VMOV (immediate) // Qd/Dd imm +// VBIC (immediate) // VORR (immediate) // Qd/Dd imm src(=Qd/Dd) static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode, @@ -2330,6 +2331,8 @@ static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode, case ARM::VMOVv8i16: case ARM::VMVNv4i16: case ARM::VMVNv8i16: + case ARM::VBICiv4i16: + case ARM::VBICiv8i16: case ARM::VORRiv4i16: case ARM::VORRiv8i16: esize = ESize16; @@ -2338,6 +2341,8 @@ static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode, case ARM::VMOVv4i32: case ARM::VMVNv2i32: case ARM::VMVNv4i32: + case ARM::VBICiv2i32: + case ARM::VBICiv4i32: case ARM::VORRiv2i32: case ARM::VORRiv4i32: esize = ESize32; @@ -2347,7 +2352,7 @@ static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode, esize = ESize64; break; default: - assert(0 && "Unreachable code!"); + assert(0 && "Unexpected opcode!"); return false; } @@ -2357,7 +2362,7 @@ static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode, NumOpsAdded = 2; - // VORRiv*i* variants have an extra $src = $Vd to be filled in. + // VBIC/VORRiv*i* variants have an extra $src = $Vd to be filled in. if (NumOps >= 3 && (OpInfo[2].RegClass == ARM::DPRRegClassID || OpInfo[2].RegClass == ARM::QPRRegClassID)) { diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index 421a8e4a5b..bd3b7d326c 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -65,3 +65,6 @@ # CHECK: vorr.i32 q15, #0x4F0000 0x5f 0xe5 0xc4 0xf2 + +# CHECK: vbic.i32 q2, #0xA900 +0x79 0x53 0x82 0xf3 |