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| author | Evan Cheng <evan.cheng@apple.com> | 2007-05-18 00:19:34 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-05-18 00:19:34 +0000 |
| commit | 9f8cbd147c0ae4ec2df0f3bbff65def0ffd784c1 (patch) | |
| tree | 08087ce62ce854f444b1a99613ce37ccfe1ae9a1 | |
| parent | 6ae3626a4fda14e6250ac8d8ff487efb8952cdf7 (diff) | |
Set ARM if-conversion block size threshold to 10 instructions for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37194 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index d30a288d19..a598fb2c8f 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -124,6 +124,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) addRegisterClass(MVT::f32, ARM::SPRRegisterClass); addRegisterClass(MVT::f64, ARM::DPRRegisterClass); } + computeRegisterProperties(); // ARM does not have f32 extending load. setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); @@ -252,9 +253,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setStackPointerRegisterToSaveRestore(ARM::SP); - setSchedulingPreference(SchedulingForRegPressure); - computeRegisterProperties(); + setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type } |