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authorJim Laskey <jlaskey@mac.com>2007-02-28 20:43:58 +0000
committerJim Laskey <jlaskey@mac.com>2007-02-28 20:43:58 +0000
commit8782d481a3c720304540254a7b71d25bbe7cbf49 (patch)
treed861930b3022ca616a834ea6c6fe07d05040e4a9
parent581b0d453a63f7f657248f80317976995262be11 (diff)
Chain is on second operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34759 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp27
1 files changed, 23 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index efff9f4828..c32311373e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -676,16 +676,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
else
Result = DAG.getConstant(0, TLI.getPointerTy());
break;
- case ISD::EHSELECTION:
case ISD::EXCEPTIONADDR: {
Tmp1 = LegalizeOp(Node->getOperand(0));
MVT::ValueType VT = Node->getValueType(0);
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
- unsigned Reg = Node->getOpcode() == ISD::EXCEPTIONADDR ?
- TLI.getExceptionAddressRegister() :
- TLI.getExceptionSelectorRegister();
+ unsigned Reg = TLI.getExceptionAddressRegister();
Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
}
break;
@@ -700,6 +697,28 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
}
}
break;
+ case ISD::EHSELECTION: {
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ Tmp2 = LegalizeOp(Node->getOperand(1));
+ MVT::ValueType VT = Node->getValueType(0);
+ switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
+ default: assert(0 && "This action is not supported yet!");
+ case TargetLowering::Expand: {
+ unsigned Reg = TLI.getExceptionSelectorRegister();
+ Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
+ }
+ break;
+ case TargetLowering::Custom:
+ Result = TLI.LowerOperation(Op, DAG);
+ if (Result.Val) break;
+ // Fall Thru
+ case TargetLowering::Legal:
+ Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp2).
+ getValue(Op.ResNo);
+ break;
+ }
+ }
+ break;
case ISD::AssertSext:
case ISD::AssertZext:
Tmp1 = LegalizeOp(Node->getOperand(0));