Add all of the necessary classes to describe the contents of the MRegister.h implementation

for a target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7415 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 40 insertions, 1 deletions

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index d8cf29c16a..d230776a31 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -5,9 +5,14 @@
 //
 //===----------------------------------------------------------------------===//
 
+
+//===----------------------------------------------------------------------===//
+//
 // Value types - These values correspond to the register types defined in the
 // ValueTypes.h file.
+
 class ValueType { string Namespace = "MVT"; }
+
 def i1   : ValueType;    // One bit boolean value
 def i8   : ValueType;    // 8-bit integer value
 def i16  : ValueType;    // 16-bit integer value
@@ -19,11 +24,45 @@ def f64  : ValueType;    // 64-bit floating point value
 def f80  : ValueType;    // 80-bit floating point value
 def f128 : ValueType;    // 128-bit floating point value
 
+
+//===----------------------------------------------------------------------===//
+// Register file description - These classes are used to fill in the target
+// description classes in llvm/Target/MRegisterInfo.h
+
+
+// Register - You should define one instance of this class for each register in
+// the target machine.
+//
 class Register {
   string Namespace = "";
-  ValueType RegType;
 }
 
+// RegisterAliases - You should define instances of this class to indicate which
+// registers in the register file are aliased together.  This allows the code
+// generator to be careful not to put two values with overlapping live ranges
+// into registers which alias.
+//
+class RegisterAliases<Register reg, list<Register> aliases> {
+  Register Reg = reg;
+  list<Register> Aliases = aliases;
+}
+
+// RegisterClass - Now that all of the registers are defined, and aliases
+// between registers are defined, specify which registers belong to which
+// register classes.  This also defines the default allocation order of
+// registers by register allocators.
+//
+class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
+  ValueType RegType = regType;
+  int Alignment = alignment;
+  list<Register> MemberList = regList;
+}
+
+
+//===----------------------------------------------------------------------===//
+// Instruction set description - 
+//
+
 class Instruction {
   string Name;          // The opcode string for this instruction
   string Namespace = "";