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authorNate Begeman <natebegeman@mac.com>2005-03-26 08:25:22 +0000
committerNate Begeman <natebegeman@mac.com>2005-03-26 08:25:22 +0000
commit7532e2f55554b9f7944a358931a22f74f8dd226e (patch)
treec88bc250a5c2f91edcbbc6c4bdaa6ee9ddbc73a3
parentf7e43380354107a925dca1a1a4d7d7e70cab04e4 (diff)
Fix that pesky floats in integer regs problem by assigning the f32 type to
the correct register class. Also remove the loading of float data into int regs part of varargs; it will need to be implemented differently later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20857 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPCISelPattern.cpp12
1 files changed, 4 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 7ec033afb8..fb00e46e6f 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -44,7 +44,7 @@ namespace {
// Set up the register classes.
addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
- addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
+ addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
computeRegisterProperties();
@@ -322,13 +322,9 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
// store only the non-fixed arguments in a vararg function.
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff));
- if (GPR_remaining > 0)
- args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
- if (GPR_remaining > 1) {
- SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
- PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
- args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
- }
+ // FIXME: Need a way to communicate to the ISD::CALL select code
+ // that a particular argument is non-fixed so that we can load them
+ // into the correct GPR to shadow the FPR
}
args_to_use.push_back(Args[i].first);
--FPR_remaining;