Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8

15 files changed, 724 insertions, 12 deletions

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 7fe0c8d3b7..f463c8aa69 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -48,47 +48,48 @@ const unsigned M_DELAY_SLOT_FLAG       = 1 << 4;
 const unsigned M_LOAD_FLAG             = 1 << 5;
 const unsigned M_STORE_FLAG            = 1 << 6;
 const unsigned M_INDIRECT_FLAG         = 1 << 7;
+const unsigned M_IMPLICIT_DEF_FLAG     = 1 << 8;
 
 // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be
 // changed into a 3-address instruction if the first two operands cannot be
 // assigned to the same register.  The target must implement the
 // TargetInstrInfo::convertToThreeAddress method for this instruction.
-const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8;
+const unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9;
 
 // This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y,
 // Z), which produces the same result if Y and Z are exchanged.
-const unsigned M_COMMUTABLE            = 1 << 9;
+const unsigned M_COMMUTABLE            = 1 << 10;
 
 // M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
 // block?  Typically this is things like return and branch instructions.
 // Various passes use this to insert code into the bottom of a basic block, but
 // before control flow occurs.
-const unsigned M_TERMINATOR_FLAG       = 1 << 10;
+const unsigned M_TERMINATOR_FLAG       = 1 << 11;
 
 // M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom
 // insertion support when the DAG scheduler is inserting it into a machine basic
 // block.
-const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11;
+const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12;
 
 // M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
 // operands in addition to the minimum number operands specified.
-const unsigned M_VARIABLE_OPS          = 1 << 12;
+const unsigned M_VARIABLE_OPS          = 1 << 13;
 
 // M_PREDICABLE - Set if this instruction has a predicate operand that
 // controls execution. It may be set to 'always'.
-const unsigned M_PREDICABLE            = 1 << 13;
+const unsigned M_PREDICABLE            = 1 << 14;
 
 // M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized
 // at any time, e.g. constant generation, load from constant pool.
-const unsigned M_REMATERIALIZIBLE      = 1 << 14;
+const unsigned M_REMATERIALIZIBLE      = 1 << 15;
 
 // M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated.
 // (e.g. instructions with unique labels attached).
-const unsigned M_NOT_DUPLICABLE        = 1 << 15;
+const unsigned M_NOT_DUPLICABLE        = 1 << 16;
 
 // M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g.
 // ARM instructions which can set condition code if 's' bit is set.
-const unsigned M_HAS_OPTIONAL_DEF      = 1 << 16;
+const unsigned M_HAS_OPTIONAL_DEF      = 1 << 17;
 
 // Machine operand flags
 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 0761e05a26..3496b6f6eb 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -613,8 +613,10 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
     return false;
 
   isLoad = false;
-  if (tii_->isTriviallyReMaterializable(MI)) {
-    isLoad = MI->getInstrDescriptor()->Flags & M_LOAD_FLAG;
+  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  if ((TID->Flags & M_IMPLICIT_DEF_FLAG) ||
+      tii_->isTriviallyReMaterializable(MI)) {
+    isLoad = TID->Flags & M_LOAD_FLAG;
     return true;
   }
 
@@ -677,6 +679,15 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
                                          bool isSS, int Slot, unsigned Reg) {
   unsigned MRInfo = 0;
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  // If it is an implicit def instruction, just delete it.
+  if (TID->Flags & M_IMPLICIT_DEF_FLAG) {
+    RemoveMachineInstrFromMaps(MI);
+    vrm.RemoveMachineInstrFromMaps(MI);
+    MI->eraseFromParent();
+    ++numFolds;
+    return true;
+  }
+
   SmallVector<unsigned, 2> FoldOps;
   for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
     unsigned OpIdx = Ops[i];
@@ -852,7 +863,8 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
       } else {
         CanFold = canFoldMemoryOperand(MI, Ops);
       }
-    } else CanFold = false;
+    } else
+      CanFold = false;
 
     // Create a new virtual register for the spill interval.
     bool CreatedNewVReg = false;
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 53c36f3a55..fd28698875 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -646,6 +646,7 @@ multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
 //===----------------------------------------------------------------------===//
 //  Miscellaneous Instructions.
 //
+let isImplicitDef = 1 in
 def IMPLICIT_DEF_GPR : 
 PseudoInst<(outs GPR:$rD), (ins pred:$p),
            "@ IMPLICIT_DEF_GPR $rD",
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 5b7a4034ef..b3fe2fff97 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -251,12 +251,14 @@ def FSQRTS  : ASI<(outs SPR:$dst), (ins SPR:$a),
 // FP <-> GPR Copies.  Int <-> FP Conversions.
 //
 
+let isImplicitDef = 1 in {
 def IMPLICIT_DEF_SPR : PseudoInst<(outs SPR:$rD), (ins pred:$p),
                                   "@ IMPLICIT_DEF_SPR $rD",
                                   [(set SPR:$rD, (undef))]>;
 def IMPLICIT_DEF_DPR : PseudoInst<(outs DPR:$rD), (ins pred:$p),
                                   "@ IMPLICIT_DEF_DPR $rD",
                                   [(set DPR:$rD, (undef))]>;
+}
 
 def FMRS   : ASI<(outs GPR:$dst), (ins SPR:$src),
                  "fmrs", " $dst, $src",
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index da24e70c18..14a9849fa6 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -141,12 +141,14 @@ class CmpOpFrag<dag res> : PatFrag<(ops node:$R), res>;
 
 //Pseudo ops for selection
 
+let isImplicitDef = 1 in {
 def IDEF_I : PseudoInstAlpha<(outs GPRC:$RA), (ins), ";#idef $RA",
              [(set GPRC:$RA, (undef))], s_pseudo>;
 def IDEF_F32 : PseudoInstAlpha<(outs F4RC:$RA), (ins), ";#idef $RA",
              [(set F4RC:$RA, (undef))], s_pseudo>;
 def IDEF_F64 : PseudoInstAlpha<(outs F8RC:$RA), (ins), ";#idef $RA",
              [(set F8RC:$RA, (undef))], s_pseudo>;
+}
 
 def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
 
diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index 8801a728f7..7df8fd807d 100644
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -457,6 +457,7 @@ def : Pat<(i1  0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
 // tablegen support
 
+let isImplicitDef = 1 in {
 def IDEF : PseudoInstIA64<(outs variable_ops), (ins), "// IDEF">;
 
 def IDEF_GR_D : PseudoInstIA64_DAG<(outs GR:$reg), (ins), "// $reg = IDEF",
@@ -465,6 +466,7 @@ def IDEF_FP_D : PseudoInstIA64_DAG<(outs FP:$reg), (ins), "// $reg = IDEF",
     [(set FP:$reg, (undef))]>;
 def IDEF_PR_D : PseudoInstIA64_DAG<(outs PR:$reg), (ins), "// $reg = IDEF",
     [(set PR:$reg, (undef))]>;
+}
 
 def IUSE : PseudoInstIA64<(outs), (ins variable_ops), "// IUSE">;
 def ADJUSTCALLSTACKUP : PseudoInstIA64<(outs), (ins variable_ops),
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index d74ca54092..4d09e8bed1 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -356,6 +356,7 @@ def ADJCALLSTACKUP   : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2),
                                       [(callseq_end imm:$amt1, imm:$amt2)]>;
 }
 
+let isImplicitDef = 1 in
 def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
                                           "!IMPLICIT_DEF $dst",
                                           [(set CPURegs:$dst, (undef))]>;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 6a53a76315..2aea2545b1 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -334,6 +334,7 @@ def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
                        [(set GPRC:$result,
                              (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
                          
+let isImplicitDef = 1 in {
 def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
                               "${:comment}IMPLICIT_DEF_GPRC $rD",
                               [(set GPRC:$rD, (undef))]>;
@@ -343,6 +344,7 @@ def IMPLICIT_DEF_F8  : Pseudo<(outs F8RC:$rD), (ins),
 def IMPLICIT_DEF_F4  : Pseudo<(outs F4RC:$rD), (ins),
                               "${:comment} IMPLICIT_DEF_F4 $rD",
                               [(set F4RC:$rD, (undef))]>;
+}
 
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded by the
 // scheduler into a branch sequence.
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 354e360059..c0b046015d 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -212,6 +212,8 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                             "!ADJCALLSTACKUP $amt1",
                             [(callseq_end imm:$amt1, imm:$amt2)]>;
 }
+
+let isImplicitDef = 1 in {
 def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
                               "!IMPLICIT_DEF $dst",
                               [(set IntRegs:$dst, (undef))]>;
@@ -219,6 +221,7 @@ def IMPLICIT_DEF_FP  : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
                               [(set FPRegs:$dst, (undef))]>;
 def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
                               [(set DFPRegs:$dst, (undef))]>;
+}
                               
 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 
 // fpmover pass.
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 4c28f99b6f..4c278bb8bd 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -192,6 +192,7 @@ class Instruction {
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit isLoad       = 0;     // Is this instruction a load instruction?
   bit isStore      = 0;     // Is this instruction a store instruction?
+  bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index a92ff50f19..75be11ba08 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -262,6 +262,7 @@ def ADJCALLSTACKUP   : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
 }
 def IMPLICIT_USE     : I<0, Pseudo, (outs), (ins variable_ops),
                          "#IMPLICIT_USE", []>;
+let isImplicitDef = 1 in {
 def IMPLICIT_DEF     : I<0, Pseudo, (outs variable_ops), (ins),
                           "#IMPLICIT_DEF", []>;
 def IMPLICIT_DEF_GR8  : I<0, Pseudo, (outs GR8:$dst), (ins),
@@ -273,6 +274,7 @@ def IMPLICIT_DEF_GR16  : I<0, Pseudo, (outs GR16:$dst), (ins),
 def IMPLICIT_DEF_GR32  : I<0, Pseudo, (outs GR32:$dst), (ins),
                          "#IMPLICIT_DEF $dst",
                          [(set GR32:$dst, (undef))]>;
+}
 
 // Nop
 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td
index c892c34233..08fa0dfe98 100644
--- a/lib/Target/X86/X86InstrMMX.td
+++ b/lib/Target/X86/X86InstrMMX.td
@@ -14,6 +14,7 @@
 //===----------------------------------------------------------------------===//
 
 // Some 'special' instructions
+let isImplicitDef = 1 in
 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
                           "#IMPLICIT_DEF $dst",
                           [(set VR64:$dst, (v8i8 (undef)))]>,
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index a196dce1b8..26767a5b61 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -42,6 +42,7 @@ def X86pinsrw  : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
 // SSE 'Special' Instructions
 //===----------------------------------------------------------------------===//
 
+let isImplicitDef = 1 in
 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
                            "#IMPLICIT_DEF $dst",
                            [(set VR128:$dst, (v4f32 (undef)))]>,
diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td
index 2d9ca97e21..6dea840134 100644
--- a/lib/Target/X86/X86InstrX86-64.td
+++ b/lib/Target/X86/X86InstrX86-64.td
@@ -80,6 +80,7 @@ def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
 // Instruction list...
 //
 
+let isImplicitDef = 1 in
 def IMPLICIT_DEF_GR64  : I<0, Pseudo, (outs GR64:$dst), (ins),
                          "#IMPLICIT_DEF $dst",
                          [(set GR64:$dst, (undef))]>;
diff --git a/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll b/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
new file mode 100644
index 0000000000..84229cf491
--- /dev/null
+++ b/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll
@@ -0,0 +1,680 @@
+; RUN: llvm-as < %s | llc -mtriple=i686-apple-darwin | not grep IMPLICIT_DEF
+
+	%struct.__sbuf = type { i8*, i32 }
+	%struct.ggBRDF = type { i32 (...)** }
+	%"struct.ggBST<ggMaterial>" = type { %"struct.ggBSTNode<ggMaterial>"*, i32 }
+	%"struct.ggBST<ggRasterSurfaceTexture>" = type { %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, i32 }
+	%"struct.ggBST<ggSolidTexture>" = type { %"struct.ggBSTNode<ggSolidTexture>"*, i32 }
+	%"struct.ggBST<ggSpectrum>" = type { %"struct.ggBSTNode<ggSpectrum>"*, i32 }
+	%"struct.ggBST<mrObjectRecord>" = type { %"struct.ggBSTNode<mrObjectRecord>"*, i32 }
+	%"struct.ggBSTNode<ggMaterial>" = type { %"struct.ggBSTNode<ggMaterial>"*, %"struct.ggBSTNode<ggMaterial>"*, %struct.ggString, %struct.ggMaterial* }
+	%"struct.ggBSTNode<ggRasterSurfaceTexture>" = type { %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, %struct.ggString, %struct.ggRasterSurfaceTexture* }
+	%"struct.ggBSTNode<ggSolidTexture>" = type { %"struct.ggBSTNode<ggSolidTexture>"*, %"struct.ggBSTNode<ggSolidTexture>"*, %struct.ggString, %struct.ggBRDF* }
+	%"struct.ggBSTNode<ggSpectrum>" = type { %"struct.ggBSTNode<ggSpectrum>"*, %"struct.ggBSTNode<ggSpectrum>"*, %struct.ggString, %struct.ggSpectrum* }
+	%"struct.ggBSTNode<mrObjectRecord>" = type { %"struct.ggBSTNode<mrObjectRecord>"*, %"struct.ggBSTNode<mrObjectRecord>"*, %struct.ggString, %struct.mrObjectRecord* }
+	%"struct.ggDictionary<ggMaterial>" = type { %"struct.ggBST<ggMaterial>" }
+	%"struct.ggDictionary<ggRasterSurfaceTexture>" = type { %"struct.ggBST<ggRasterSurfaceTexture>" }
+	%"struct.ggDictionary<ggSolidTexture>" = type { %"struct.ggBST<ggSolidTexture>" }
+	%"struct.ggDictionary<ggSpectrum>" = type { %"struct.ggBST<ggSpectrum>" }
+	%"struct.ggDictionary<mrObjectRecord>" = type { %"struct.ggBST<mrObjectRecord>" }
+	%struct.ggHAffineMatrix3 = type { %struct.ggHMatrix3 }
+	%struct.ggHBoxMatrix3 = type { %struct.ggHAffineMatrix3 }
+	%struct.ggHMatrix3 = type { [4 x [4 x double]] }
+	%struct.ggMaterial = type { i32 (...)**, %struct.ggBRDF* }
+	%struct.ggPoint3 = type { [3 x double] }
+	%"struct.ggRGBPixel<char>" = type { [3 x i8], i8 }
+	%"struct.ggRaster<ggRGBPixel<unsigned char> >" = type { i32, i32, %"struct.ggRGBPixel<char>"* }
+	%struct.ggRasterSurfaceTexture = type { %"struct.ggRaster<ggRGBPixel<unsigned char> >"* }
+	%struct.ggSolidNoise3 = type { i32, [256 x %struct.ggPoint3], [256 x i32] }
+	%struct.ggSpectrum = type { [8 x float] }
+	%struct.ggString = type { %"struct.ggString::StringRep"* }
+	%"struct.ggString::StringRep" = type { i32, i32, [1 x i8] }
+	%"struct.ggTrain<mrPixelRenderer*>" = type { %struct.ggBRDF**, i32, i32 }
+	%struct.mrObjectRecord = type { %struct.ggHBoxMatrix3, %struct.ggHBoxMatrix3, %struct.mrSurfaceList, %struct.ggMaterial*, i32, %struct.ggRasterSurfaceTexture*, %struct.ggBRDF*, i32, i32 }
+	%struct.mrScene = type { %struct.ggSpectrum, %struct.ggSpectrum, %struct.ggBRDF*, %struct.ggBRDF*, %struct.ggBRDF*, i32, double, %"struct.ggDictionary<mrObjectRecord>", %"struct.ggDictionary<ggRasterSurfaceTexture>", %"struct.ggDictionary<ggSolidTexture>", %"struct.ggDictionary<ggSpectrum>", %"struct.ggDictionary<ggMaterial>" }
+	%struct.mrSurfaceList = type { %struct.ggBRDF, %"struct.ggTrain<mrPixelRenderer*>" }
+	%"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>" = type { %"struct.std::locale::facet" }
+	%"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>"*, %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>"* }
+	%"struct.std::basic_istream<char,std::char_traits<char> >" = type { i32 (...)**, i32, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+	%"struct.std::basic_ostream<char,std::char_traits<char> >" = type { i32 (...)**, %"struct.std::basic_ios<char,std::char_traits<char> >" }
+	%"struct.std::basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" }
+	%"struct.std::ctype<char>" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 }
+	%"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %struct.__sbuf, [8 x %struct.__sbuf], i32, %struct.__sbuf*, %"struct.std::locale" }
+	%"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 }
+	%"struct.std::locale" = type { %"struct.std::locale::_Impl"* }
+	%"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** }
+	%"struct.std::locale::facet" = type { i32 (...)**, i32 }
+@.str80 = external constant [7 x i8]		; <[7 x i8]*> [#uses=1]
+@.str81 = external constant [11 x i8]		; <[11 x i8]*> [#uses=1]
+
+define fastcc void @_ZN7mrScene4ReadERSi(%struct.mrScene* %this, %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces) {
+entry:
+	%tmp6.i.i8288 = invoke i8* @_Znam( i32 12 )
+			to label %_ZN8ggStringC1Ei.exit unwind label %lpad		; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit:		; preds = %entry
+	%tmp6.i.i8995 = invoke i8* @_Znam( i32 12 )
+			to label %_ZN8ggStringC1Ei.exit96 unwind label %lpad3825		; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit96:		; preds = %_ZN8ggStringC1Ei.exit
+	%tmp6.i.i97103 = invoke i8* @_Znam( i32 12 )
+			to label %_ZN8ggStringC1Ei.exit104 unwind label %lpad3829		; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit104:		; preds = %_ZN8ggStringC1Ei.exit96
+	%tmp6.i.i105111 = invoke i8* @_Znam( i32 12 )
+			to label %_ZN8ggStringC1Ei.exit112 unwind label %lpad3833		; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit112:		; preds = %_ZN8ggStringC1Ei.exit104
+	%tmp6.i.i122128 = invoke i8* @_Znam( i32 12 )
+			to label %_ZN8ggStringC1Ei.exit129 unwind label %lpad3837		; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit129:		; preds = %_ZN8ggStringC1Ei.exit112
+	%tmp6.i.i132138 = invoke i8* @_Znam( i32 12 )
+			to label %_ZN8ggStringC1Ei.exit139 unwind label %lpad3841		; <i8*> [#uses=0]
+
+_ZN8ggStringC1Ei.exit139:		; preds = %_ZN8ggStringC1Ei.exit129
+	%tmp295 = invoke i8* @_Znwm( i32 16 )
+			to label %invcont294 unwind label %lpad3845		; <i8*> [#uses=0]
+
+invcont294:		; preds = %_ZN8ggStringC1Ei.exit139
+	%tmp10.i.i141 = invoke i8* @_Znam( i32 16 )
+			to label %_ZN13mrSurfaceListC1Ev.exit unwind label %lpad3849		; <i8*> [#uses=0]
+
+_ZN13mrSurfaceListC1Ev.exit:		; preds = %invcont294
+	%tmp3.i148 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+			to label %tmp3.i.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i.noexc:		; preds = %_ZN13mrSurfaceListC1Ev.exit
+	%tmp15.i149 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+			to label %tmp15.i.noexc unwind label %lpad3845		; <i8*> [#uses=0]
+
+tmp15.i.noexc:		; preds = %tmp3.i.noexc
+	br i1 false, label %bb308, label %bb.i
+
+bb.i:		; preds = %tmp15.i.noexc
+	ret void
+
+bb308:		; preds = %tmp15.i.noexc
+	br i1 false, label %bb3743.preheader, label %bb315
+
+bb3743.preheader:		; preds = %bb308
+	%tmp16.i3862 = getelementptr %struct.ggPoint3* null, i32 0, i32 0, i32 0		; <double*> [#uses=1]
+	%tmp16.i3859 = getelementptr %struct.ggPoint3* null, i32 0, i32 0, i32 0		; <double*> [#uses=3]
+	br label %bb3743
+
+bb315:		; preds = %bb308
+	ret void
+
+bb333:		; preds = %invcont3758, %invcont335
+	%tmp3.i167180 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+			to label %tmp3.i167.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i167.noexc:		; preds = %bb333
+	%tmp15.i182 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+			to label %tmp15.i.noexc181 unwind label %lpad3845		; <i8*> [#uses=0]
+
+tmp15.i.noexc181:		; preds = %tmp3.i167.noexc
+	br i1 false, label %invcont335, label %bb.i178
+
+bb.i178:		; preds = %tmp15.i.noexc181
+	ret void
+
+invcont335:		; preds = %tmp15.i.noexc181
+	br i1 false, label %bb3743, label %bb333
+
+bb345:		; preds = %invcont3758
+	br i1 false, label %bb353, label %bb360
+
+bb353:		; preds = %bb345
+	%tmp356 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+			to label %bb3743 unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+bb360:		; preds = %bb345
+	br i1 false, label %bb368, label %bb374
+
+bb368:		; preds = %bb360
+	%tmp373 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+			to label %bb3743 unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+bb374:		; preds = %bb360
+	br i1 false, label %bb396, label %bb421
+
+bb396:		; preds = %bb374
+	ret void
+
+bb421:		; preds = %bb374
+	br i1 false, label %bb429, label %bb530
+
+bb429:		; preds = %bb421
+	ret void
+
+bb530:		; preds = %bb421
+	br i1 false, label %bb538, label %bb673
+
+bb538:		; preds = %bb530
+	ret void
+
+bb673:		; preds = %bb530
+	br i1 false, label %bb681, label %bb778
+
+bb681:		; preds = %bb673
+	ret void
+
+bb778:		; preds = %bb673
+	br i1 false, label %bb786, label %bb891
+
+bb786:		; preds = %bb778
+	ret void
+
+bb891:		; preds = %bb778
+	br i1 false, label %bb899, label %bb998
+
+bb899:		; preds = %bb891
+	ret void
+
+bb998:		; preds = %bb891
+	br i1 false, label %bb1168, label %bb1190
+
+bb1168:		; preds = %bb998
+	ret void
+
+bb1190:		; preds = %bb998
+	br i1 false, label %bb1198, label %bb1220
+
+bb1198:		; preds = %bb1190
+	ret void
+
+bb1220:		; preds = %bb1190
+	br i1 false, label %bb1228, label %bb1250
+
+bb1228:		; preds = %bb1220
+	ret void
+
+bb1250:		; preds = %bb1220
+	br i1 false, label %bb1258, label %bb1303
+
+bb1258:		; preds = %bb1250
+	ret void
+
+bb1303:		; preds = %bb1250
+	br i1 false, label %bb1311, label %bb1366
+
+bb1311:		; preds = %bb1303
+	ret void
+
+bb1366:		; preds = %bb1303
+	br i1 false, label %bb1374, label %bb1432
+
+bb1374:		; preds = %bb1366
+	ret void
+
+bb1432:		; preds = %bb1366
+	br i1 false, label %bb1440, label %bb1495
+
+bb1440:		; preds = %bb1432
+	ret void
+
+bb1495:		; preds = %bb1432
+	br i1 false, label %bb1503, label %bb1561
+
+bb1503:		; preds = %bb1495
+	ret void
+
+bb1561:		; preds = %bb1495
+	br i1 false, label %bb1569, label %bb1624
+
+bb1569:		; preds = %bb1561
+	ret void
+
+bb1624:		; preds = %bb1561
+	br i1 false, label %bb1632, label %bb1654
+
+bb1632:		; preds = %bb1624
+	store double 0.000000e+00, double* %tmp16.i3859, align 8
+	%tmp3.i38383852 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+			to label %tmp3.i3838.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3838.noexc:		; preds = %bb1632
+	%tmp15.i38473853 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+			to label %tmp15.i3847.noexc unwind label %lpad3845		; <i8*> [#uses=0]
+
+tmp15.i3847.noexc:		; preds = %tmp3.i3838.noexc
+	br i1 false, label %invcont1634, label %bb.i3850
+
+bb.i3850:		; preds = %tmp15.i3847.noexc
+	ret void
+
+invcont1634:		; preds = %tmp15.i3847.noexc
+	%tmp3.i38173831 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+			to label %tmp3.i3817.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3817.noexc:		; preds = %invcont1634
+	%tmp15.i38263832 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+			to label %tmp15.i3826.noexc unwind label %lpad3845		; <i8*> [#uses=0]
+
+tmp15.i3826.noexc:		; preds = %tmp3.i3817.noexc
+	br i1 false, label %invcont1636, label %bb.i3829
+
+bb.i3829:		; preds = %tmp15.i3826.noexc
+	ret void
+
+invcont1636:		; preds = %tmp15.i3826.noexc
+	%tmp8.i38083811 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* %tmp16.i3862 )
+			to label %tmp8.i3808.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp8.i3808.noexc:		; preds = %invcont1636
+	%tmp9.i38093812 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i38083811, double* null )
+			to label %tmp9.i3809.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp9.i3809.noexc:		; preds = %tmp8.i3808.noexc
+	%tmp10.i38103813 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i38093812, double* null )
+			to label %invcont1638 unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont1638:		; preds = %tmp9.i3809.noexc
+	%tmp8.i37983801 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* %tmp16.i3859 )
+			to label %tmp8.i3798.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp8.i3798.noexc:		; preds = %invcont1638
+	%tmp9.i37993802 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i37983801, double* null )
+			to label %tmp9.i3799.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+tmp9.i3799.noexc:		; preds = %tmp8.i3798.noexc
+	%tmp10.i38003803 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i37993802, double* null )
+			to label %invcont1640 unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+invcont1640:		; preds = %tmp9.i3799.noexc
+	%tmp3.i3778 = load double* %tmp16.i3859, align 8		; <double> [#uses=1]
+	%tmp1643 = invoke i8* @_Znwm( i32 76 )
+			to label %invcont1642 unwind label %lpad3845		; <i8*> [#uses=0]
+
+invcont1642:		; preds = %invcont1640
+	%tmp18.i3770 = sub double %tmp3.i3778, 0.000000e+00		; <double> [#uses=0]
+	invoke fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i( %struct.mrScene* %this, %struct.ggBRDF* null, %struct.ggString* null, %struct.ggString* null, i32 0 )
+			to label %bb3743 unwind label %lpad3845
+
+bb1654:		; preds = %bb1624
+	br i1 false, label %bb1662, label %bb1693
+
+bb1662:		; preds = %bb1654
+	%tmp3.i37143728 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+			to label %tmp3.i3714.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3714.noexc:		; preds = %bb1662
+	%tmp15.i37233729 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+			to label %tmp15.i3723.noexc unwind label %lpad3845		; <i8*> [#uses=0]
+
+tmp15.i3723.noexc:		; preds = %tmp3.i3714.noexc
+	ret void
+
+bb1693:		; preds = %bb1654
+	br i1 false, label %bb1701, label %bb1745
+
+bb1701:		; preds = %bb1693
+	%tmp3.i36493663 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+			to label %tmp3.i3649.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3649.noexc:		; preds = %bb1701
+	ret void
+
+bb1745:		; preds = %bb1693
+	br i1 false, label %bb1753, label %bb1797
+
+bb1753:		; preds = %bb1745
+	ret void
+
+bb1797:		; preds = %bb1745
+	br i1 false, label %bb1805, label %bb1847
+
+bb1805:		; preds = %bb1797
+	ret void
+
+bb1847:		; preds = %bb1797
+	br i1 false, label %bb1855, label %bb1897
+
+bb1855:		; preds = %bb1847
+	%tmp3.i34633477 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null )
+			to label %tmp3.i3463.noexc unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0]
+
+tmp3.i3463.noexc:		; preds = %bb1855
+	%tmp15.i34723478 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null )
+			to label %tmp15.i3472.noexc unwind label %lpad3845		; <i8*> [#uses=0]
+
+tmp15.i3472.noexc:		; preds = %tmp3.i3463.noexc
+	br i1 false, label %invcont1857, label %bb.i3475
+
+bb.i3475:		; preds = %tmp15.i3472.noexc
+	invoke fastcc void @_ZN8ggStringaSEPKc( %struct.ggString* null, i8* null )
+			to label %invcont1857 unwind label %lpad3845
+
+invcont1857:		; preds = %bb.i3475, %tmp15.i3472.noexc
+	%tmp1860 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null )
+			to label %invcont1859 unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+
+invcont1859:		; preds = %invcont1857
+	%tmp1862 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1860, double* null )
+			to label %invcont1861 unwind label %lpad3845		; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1]
+