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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-09-02 21:21:28 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-09-02 21:21:28 +0000 |
| commit | 69d1c1aebf009e58157e233cd7f2338e654e8d05 (patch) | |
| tree | 64d319e39923fa597ac936981ee5c27afd986669 | |
| parent | 778b06bbcecbe52125dddcb06e898806b1e2b3c7 (diff) | |
More missed vdup patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80838 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 12 | ||||
| -rw-r--r-- | test/CodeGen/ARM/vdup_lane.ll | 24 |
2 files changed, 36 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 0c2f65523b..c111668c5b 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -355,6 +355,9 @@ def DSubReg_i32_reg : SDNodeXForm<imm, [{ def DSubReg_f64_reg : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32); }]>; +def DSubReg_f64_other_reg : SDNodeXForm<imm, [{ + return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32); +}]>; // Extract S sub-registers of Q/D registers. // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.) @@ -1907,6 +1910,15 @@ def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0, NoItinerary, "vdup.32\t$dst, ${src:lane}", "", [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>; +def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)), + (INSERT_SUBREG QPR:$src, + (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))), + (DSubReg_f64_other_reg imm:$lane))>; +def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)), + (INSERT_SUBREG QPR:$src, + (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))), + (DSubReg_f64_other_reg imm:$lane))>; + // VMOVN : Vector Narrowing Move defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i", int_arm_neon_vmovn>; diff --git a/test/CodeGen/ARM/vdup_lane.ll b/test/CodeGen/ARM/vdup_lane.ll index adadc9f5d3..c14f864c48 100644 --- a/test/CodeGen/ARM/vdup_lane.ll +++ b/test/CodeGen/ARM/vdup_lane.ll @@ -50,3 +50,27 @@ define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ret <4 x float> %tmp2 } + +define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { +entry: + %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1> + ret <2 x i64> %0 +} + +define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { +entry: + %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> + ret <2 x i64> %0 +} + +define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { +entry: + %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1> + ret <2 x double> %0 +} + +define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { +entry: + %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0> + ret <2 x double> %0 +}
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