diff options
author | Chris Lattner <sabre@nondot.org> | 2003-04-25 05:23:10 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2003-04-25 05:23:10 +0000 |
commit | 4deaf3b5c0f3aba5ea663e0be1721b316f542ba6 (patch) | |
tree | b08cc53d55327aee80dc9598912a9e02ce198909 | |
parent | 2b5f2c1a648895d4075f0f35c8a37bd485b9eab0 (diff) |
Fix obvious type-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5932 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/SparcV9/SparcV9InstrInfo.cpp | 2 | ||||
-rw-r--r-- | lib/Target/SparcV9/SparcV9InstrSelection.cpp | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp index 6df7617c93..8bdb0f2966 100644 --- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp +++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp @@ -443,7 +443,7 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target, if (opSize > destSize || (val->getType()->isSigned() - && destSize < target.getTargetData().getIntegerRegize())) + && destSize < target.getTargetData().getIntegerRegSize())) { // operand is larger than dest, // OR both are equal but smaller than the full register size // AND operand is signed, so it may have extra sign bits: diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp index 73e3b1ce6f..50e2fe23d4 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp +++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp @@ -759,7 +759,7 @@ CreateShiftInstructions(const TargetMachine& target, Value* shiftDest = destVal; unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType()); if ((shiftOpCode == SLL || shiftOpCode == SLLX) - && opSize < target.getTargetData().getIntegerRegize()) + && opSize < target.getTargetData().getIntegerRegSize()) { // put SLL result into a temporary shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp"); mcfi.addTemp(shiftDest); @@ -2305,7 +2305,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, .addReg(dest, MOTy::Def); mvec.push_back(M); } - else if (destSize < target.getTargetData().getIntegerRegize()) + else if (destSize < target.getTargetData().getIntegerRegSize()) assert(0 && "Unsupported type size: 32 < size < 64 bits"); } } |