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authorRafael Espindola <rafael.espindola@gmail.com>2006-10-06 12:50:22 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-10-06 12:50:22 +0000
commit4a408d46d4c2d9a7e5598c9a96886374ca7044f6 (patch)
tree15b8f1f7a9fdeb3baca36eb3a60866f62aac4adc
parenta26eb5e1a7e36521caff281da687764a0c43e428 (diff)
add support for calling functions that have double arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30765 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp29
-rw-r--r--test/CodeGen/ARM/fp.ll10
2 files changed, 30 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 25892d83c6..107ce5c543 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -265,16 +265,31 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
// and flag operands which copy the outgoing args into the appropriate regs.
SDOperand InFlag;
for (unsigned i = 0, e = Layout.lastRegArg(); i <= e; ++i) {
- SDOperand Arg = Op.getOperand(5+2*i);
- unsigned Reg = regs[Layout.getRegisterNum(i)];
- assert(Layout.getType(i) == Arg.getValueType());
- assert(Layout.getType(i) == MVT::i32);
- Chain = DAG.getCopyToReg(Chain, Reg, Arg, InFlag);
- InFlag = Chain.getValue(1);
+ SDOperand Arg = Op.getOperand(5+2*i);
+ unsigned RegNum = Layout.getRegisterNum(i);
+ unsigned Reg1 = regs[RegNum];
+ MVT::ValueType VT = Layout.getType(i);
+ assert(VT == Arg.getValueType());
+ assert(VT == MVT::i32 || VT == MVT::f32 || VT == MVT::f64);
// Add argument register to the end of the list so that it is known live
// into the call.
- Ops.push_back(DAG.getRegister(Reg, Arg.getValueType()));
+ Ops.push_back(DAG.getRegister(Reg1, MVT::i32));
+ if (VT == MVT::f64) {
+ unsigned Reg2 = regs[RegNum + 1];
+ SDOperand SDReg1 = DAG.getRegister(Reg1, MVT::i32);
+ SDOperand SDReg2 = DAG.getRegister(Reg2, MVT::i32);
+
+ Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
+ SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg}; //missing flag
+ Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
+ } else {
+ if (VT == MVT::f32)
+ Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);
+ Chain = DAG.getCopyToReg(Chain, Reg1, Arg, InFlag);
+ }
+ InFlag = Chain.getValue(1);
}
std::vector<MVT::ValueType> NodeTys;
diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll
index 313e83f256..22382ea185 100644
--- a/test/CodeGen/ARM/fp.ll
+++ b/test/CodeGen/ARM/fp.ll
@@ -3,8 +3,8 @@
; RUN: llvm-as < %s | llc -march=arm | grep fsitos &&
; RUN: llvm-as < %s | llc -march=arm | grep fmrs &&
; RUN: llvm-as < %s | llc -march=arm | grep fsitod &&
-; RUN: llvm-as < %s | llc -march=arm | grep fmrrd | wc -l | grep 2 &&
-; RUN: llvm-as < %s | llc -march=arm | grep fmdrr | wc -l | grep 1 &&
+; RUN: llvm-as < %s | llc -march=arm | grep fmrrd | wc -l | grep 3 &&
+; RUN: llvm-as < %s | llc -march=arm | grep fmdrr | wc -l | grep 2 &&
; RUN: llvm-as < %s | llc -march=arm | grep flds &&
; RUN: llvm-as < %s | llc -march=arm | grep ".word.*1065353216"
@@ -28,3 +28,9 @@ entry:
double %f2(double %a) {
ret double %a
}
+
+void %f3(double %a) {
+ call void %f4( double %a)
+ ret void
+}
+declare void %f4(double)