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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-17 19:55:51 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-17 19:55:51 +0000 |
| commit | 4372ca6fe4119d708d43d9c9ac3feafc7607952a (patch) | |
| tree | eba10fa308a2237f39797fb6ca82c96242f12189 | |
| parent | 8884148b8e8f19d5484e735618cf188cfa02c626 (diff) | |
80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137857 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Thumb1RegisterInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 53476def9d..dd066e891c 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -240,7 +240,8 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB, Bytes -= ThisVal; const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); const MachineInstrBuilder MIB = - AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg).setMIFlags(MIFlags)); + AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) + .setMIFlags(MIFlags)); AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); } else { AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) |