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authorChris Lattner <sabre@nondot.org>2005-10-21 22:15:43 +0000
committerChris Lattner <sabre@nondot.org>2005-10-21 22:15:43 +0000
commit4245f1d79068e589f8db5972917b2e393b60cc7d (patch)
treef155e774a0ea8b3266d07302739fadc0cdcda968
parentc8597ca6985f8de7ab4398f60b0be1e1bea3a5b9 (diff)
64-bit reg support should not be enabled by default, as support isn't complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23878 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/PowerPC/PPC.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
index cfe2b5f8ed..c714c913fb 100644
--- a/lib/Target/PowerPC/PPC.td
+++ b/lib/Target/PowerPC/PPC.td
@@ -57,12 +57,12 @@ def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"750", G3Itineraries, []>;
def : Processor<"970", G5Itineraries,
[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
- Feature64Bit, Feature64BitRegs]>;
+ Feature64Bit /*, Feature64BitRegs*/]>;
def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
def : Processor<"g5", G5Itineraries,
[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
- Feature64Bit, Feature64BitRegs]>;
+ Feature64Bit /*, Feature64BitRegs*/]>;
def : Processor<"generic", G3Itineraries, []>;