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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-17 22:57:40 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-17 22:57:40 +0000 |
| commit | 395b453bed53a60c559b679eb92f75d0b140b307 (patch) | |
| tree | 07ad4ebfd212c198e619afe9ecb467bf70f7fe18 | |
| parent | f6d3a4c7c4d14ad7a4e07e9f80f94f73651960d8 (diff) | |
Thumb assembly parsing and encoding for B.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 4 | ||||
| -rw-r--r-- | test/MC/ARM/basic-thumb-instructions.s | 12 |
2 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 74d34e1443..f89968f670 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3035,6 +3035,10 @@ processInstruction(MCInst &Inst, if (Inst.getOperand(3).getImm() < 8) Inst.setOpcode(ARM::tADDi3); break; + case ARM::tBcc: + // If the conditional is AL, we really want tB. + if (Inst.getOperand(1).getImm() == ARMCC::AL) + Inst.setOpcode(ARM::tB); } } diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s index 7899a550f2..f690c55b74 100644 --- a/test/MC/ARM/basic-thumb-instructions.s +++ b/test/MC/ARM/basic-thumb-instructions.s @@ -76,3 +76,15 @@ _func: asrs r5, r2 @ CHECK: asrs r5, r2 @ encoding: [0x15,0x41] + + +@------------------------------------------------------------------------------ +@ B +@------------------------------------------------------------------------------ + b _baz + beq _bar + +@ CHECK: b _baz @ encoding: [A,0xe0'A'] + @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br +@ CHECK: beq _bar @ encoding: [A,0xd0] + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc |