diff options
| author | Brian Gaeke <gaeke@uiuc.edu> | 2003-09-16 15:38:05 +0000 |
|---|---|---|
| committer | Brian Gaeke <gaeke@uiuc.edu> | 2003-09-16 15:38:05 +0000 |
| commit | 305f02dd6494147904f684621138cf0fe55bc41e (patch) | |
| tree | f31723df8a1112d15c086c64a6044ab732c2c0de | |
| parent | e655a637a717052e5d107d30a0981289c39234ad (diff) | |
Fix typo in comment. Take out some random whitespace.
(Partial merge from my working file)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8564 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/RegAlloc/PhyRegAlloc.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp | 5 |
2 files changed, 2 insertions, 8 deletions
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp index a04d4b8cda..6cb241a37a 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp @@ -1397,18 +1397,16 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() { //---------------------------------------------------------------------------- -// The entry pont to Register Allocation +// The entry point to Register Allocation //---------------------------------------------------------------------------- void PhyRegAlloc::allocateRegisters() { - // make sure that we put all register classes into the RegClassList // before we call constructLiveRanges (now done in the constructor of // PhyRegAlloc class). // LRI.constructLiveRanges(); // create LR info - if (DEBUG_RA >= RA_DEBUG_LiveRanges) LRI.printLiveRanges(); @@ -1416,7 +1414,6 @@ void PhyRegAlloc::allocateRegisters() buildInterferenceGraphs(); // build IGs in all reg classes - if (DEBUG_RA >= RA_DEBUG_LiveRanges) { // print all LRs in all reg classes for ( unsigned rc=0; rc < NumOfRegClasses ; rc++) diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index a04d4b8cda..6cb241a37a 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -1397,18 +1397,16 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() { //---------------------------------------------------------------------------- -// The entry pont to Register Allocation +// The entry point to Register Allocation //---------------------------------------------------------------------------- void PhyRegAlloc::allocateRegisters() { - // make sure that we put all register classes into the RegClassList // before we call constructLiveRanges (now done in the constructor of // PhyRegAlloc class). // LRI.constructLiveRanges(); // create LR info - if (DEBUG_RA >= RA_DEBUG_LiveRanges) LRI.printLiveRanges(); @@ -1416,7 +1414,6 @@ void PhyRegAlloc::allocateRegisters() buildInterferenceGraphs(); // build IGs in all reg classes - if (DEBUG_RA >= RA_DEBUG_LiveRanges) { // print all LRs in all reg classes for ( unsigned rc=0; rc < NumOfRegClasses ; rc++) |