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| author | Richard Smith <richard-llvm@metafoo.co.uk> | 2012-04-16 18:43:53 +0000 |
|---|---|---|
| committer | Richard Smith <richard-llvm@metafoo.co.uk> | 2012-04-16 18:43:53 +0000 |
| commit | 2c651fe6f445724627dcc48064797dca2aa4aedc (patch) | |
| tree | 514abd014bad9b9592d08dbef18b782f651d2dba | |
| parent | 1fbfea7b06928efe822b12a1d1d0af01fe2f50d1 (diff) | |
Fix incorrect atomics codegen introduced in r154705, and extend test to catch it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154845 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/atomic_op.ll | 13 |
2 files changed, 10 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index c0e935df58..8418bb12b9 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -11420,7 +11420,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, t3 = t2; MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); - MIB.addReg(t3); + MIB.addReg(t1); MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); for (int i=0; i <= lastAddrIndx; ++i) diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll index c8cb78e34e..7c5abe2095 100644 --- a/test/CodeGen/X86/atomic_op.ll +++ b/test/CodeGen/X86/atomic_op.ll @@ -107,10 +107,15 @@ entry: ; CHECK: cmpxchgl %17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic store i32 %17, i32* %old - ; CHECK: andl - ; CHECK: notl - ; CHECK: lock - ; CHECK: cmpxchgl + ; CHECK: movl $1401, %[[R17mask:[a-z]*]] + ; CHECK: movl [[R17atomic:.*]], %eax + ; CHECK: movl %eax, %[[R17newval:[a-z]*]] + ; CHECK: andl %[[R17mask]], %[[R17newval]] + ; CHECK: notl %[[R17newval]] + ; CHECK: lock + ; CHECK: cmpxchgl %[[R17newval]], [[R17atomic]] + ; CHECK: jne + ; CHECK: movl %eax, %18 = atomicrmw nand i32* %val2, i32 1401 monotonic store i32 %18, i32* %old ; CHECK: andl |