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| author | Evan Cheng <evan.cheng@apple.com> | 2007-07-13 23:55:50 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-13 23:55:50 +0000 |
| commit | 03494d7c8ff981a7466da89fd6798313b2fb222e (patch) | |
| tree | 971145807ea47c96bb826e8aa4510d10fee501c2 | |
| parent | a08971559d6393307070ec970e35240eb0598deb (diff) | |
Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39843 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index 11251e9258..8e2f4444b8 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -26,9 +26,9 @@ class Rf<bits<5> num, string n> : SparcReg<n> { let Num = num; } // Rd - Slots in the FP register file for 64-bit floating-point values. -class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> { +class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { let Num = num; - let Aliases = aliases; + let SubRegs = subregs; } // Integer registers |