diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-09-15 21:04:54 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-09-15 21:04:54 +0000 |
| commit | 60396975bea44c8d233eb11df2eb7599d2f5fa90 (patch) | |
| tree | e2b6d9254984557fac90431f349ec69db1f92b24 | |
| parent | a4c3c8f28d9465dc7c42eb43c2377530f1821574 (diff) | |
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 15 | ||||
| -rw-r--r-- | test/MC/Disassembler/neon-tests.txt | 2 |
2 files changed, 9 insertions, 8 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index edfb20766c..4dc16bb72f 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1573,8 +1573,7 @@ static unsigned decodeVFPRm(uint32_t insn, bool isSPVFP) { } // A7.5.1 -#if 0 -static uint64_t VFPExpandImm(unsigned char byte, unsigned N) { +static APInt VFPExpandImm(unsigned char byte, unsigned N) { assert(N == 32 || N == 64); uint64_t Result; @@ -1593,9 +1592,8 @@ static uint64_t VFPExpandImm(unsigned char byte, unsigned N) { else Result |= 0x1L << 62; } - return Result; + return APInt(N, Result); } -#endif // VFP Unary Format Instructions: // @@ -1972,10 +1970,11 @@ static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, // Extract/decode the f64/f32 immediate. if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { - // The asm syntax specifies the before-expanded <imm>. - // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0), - // Opcode == ARM::FCONSTD ? 64 : 32) - MI.addOperand(MCOperand::CreateImm(slice(insn,19,16)<<4 | slice(insn,3,0))); + // The asm syntax specifies the floating point value, not the 8-bit literal. + APInt immRaw = VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0), + Opcode == ARM::FCONSTD ? 64 : 32); + MI.addOperand(MCOperand::CreateFPImm(APFloat(immRaw, true))); + ++OpIdx; } diff --git a/test/MC/Disassembler/neon-tests.txt b/test/MC/Disassembler/neon-tests.txt index 35d4bd4da9..c6e16216bf 100644 --- a/test/MC/Disassembler/neon-tests.txt +++ b/test/MC/Disassembler/neon-tests.txt @@ -51,3 +51,5 @@ # CHECK: vtbx.8 d18, {d4, d5, d6}, d7 0x47 0x2a 0xf4 0xf3 +# CHECK: vmov.f32 s0, #5.000000e-01 +0x00 0x0a 0xb6 0xee |