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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-08-13 17:44:10 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-08-13 17:44:10 +0000 |
| commit | bbadd39bbbf0a79188b5688b830e6888f946a4bb (patch) | |
| tree | bcb6c2106077deaeffe365effdfef825e4e4c433 | |
| parent | c92bb50a0cdecccfa53573df720d5893f83f615e (diff) | |
Improve comment to make explicit why not to touch this could before JIT goes MC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111021 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 6cddc55eb4..1257651c6a 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2174,7 +2174,9 @@ def : Pat<(X86SFence), (SFENCE)>; // Alias instructions that map zero vector to pxor / xorp* for sse. // We set canFoldAsLoad because this can be converted to a constant-pool // load of an all-zeros value if folding it would be beneficial. -// FIXME: Change encoding to pseudo! +// FIXME: Change encoding to pseudo! This is blocked right now by the x86 +// JIT implementatioan, it does not expand the instructions below like +// X86MCInstLower does. let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, isCodeGenOnly = 1 in { def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", @@ -2188,6 +2190,9 @@ def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", // The same as done above but for AVX. The 128-bit versions are the // same, but re-encoded. The 256-bit does not support PI version. +// FIXME: Change encoding to pseudo! This is blocked right now by the x86 +// JIT implementatioan, it does not expand the instructions below like +// X86MCInstLower does. let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, isCodeGenOnly = 1, Predicates = [HasAVX] in { def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", |