Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start

checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113031 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 23 insertions, 4 deletions

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index d89f2baf2d..4b4575813a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5475,10 +5475,29 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
   if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
     return CommuteVectorShuffle(SVOp, DAG);
 
-  // Check for legal shuffle and return?
-  SmallVector<int, 16> PermMask;
-  SVOp->getMask(PermMask);
-  if (isShuffleMaskLegal(PermMask, VT))
+  // The checks below are all present in isShuffleMaskLegal, but they are
+  // inlined here right now to enable us to directly emit target specific
+  // nodes, and remove one by one until they don't return Op anymore.
+  SmallVector<int, 16> M;
+  SVOp->getMask(M);
+
+  // Very little shuffling can be done for 64-bit vectors right now.
+  if (VT.getSizeInBits() == 64)
+    return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ? Op : SDValue();
+
+  // FIXME: pshufb, blends, shifts.
+  if (VT.getVectorNumElements() == 2 ||
+      ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
+      isMOVLMask(M, VT) ||
+      isSHUFPMask(M, VT) ||
+      isPSHUFDMask(M, VT) ||
+      isPSHUFHWMask(M, VT) ||
+      isPSHUFLWMask(M, VT) ||
+      isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
+      isUNPCKLMask(M, VT) ||
+      isUNPCKHMask(M, VT) ||
+      isUNPCKL_v_undef_Mask(M, VT) ||
+      isUNPCKH_v_undef_Mask(M, VT))
     return Op;
 
   // Handle v8i16 specifically since SSE can do byte extraction and insertion.