80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50266 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 1 deletions

diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp
index 3aa40dc3e0..9c8de12108 100644
--- a/lib/Target/TargetRegisterInfo.cpp
+++ b/lib/Target/TargetRegisterInfo.cpp
@@ -54,7 +54,7 @@ TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg,
 
   // Pick the register class of the right type that contains this physreg.
   SmallVector<const TargetRegisterClass*, 4> RCs;
-  for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) {
+  for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
     if ((VT == MVT::Other || (*I)->hasType(VT)) && (*I)->contains(reg))
       RCs.push_back(*I);
   }