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authorBill Wendling <isanbard@gmail.com>2010-09-29 23:07:19 +0000
committerBill Wendling <isanbard@gmail.com>2010-09-29 23:07:19 +0000
commit15c8c33d52dbaaef8d0334051d846e38edd50231 (patch)
treebed2d99ce23196f1afc921e55774f7fc415d17ab
parent0d62b9a9a8b46caebfbe560368dcae7e0134a3a0 (diff)
Merge in r114506.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_28@115101 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMBaseInstrInfo.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 3a8bebe0dd..e4f10f93fb 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1389,7 +1389,8 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
// Check that CPSR isn't set between the comparison instruction and the one we
// want to change.
- MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
+ MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
+ B = MI->getParent()->begin();
--I;
for (; I != E; --I) {
const MachineInstr &Instr = *I;
@@ -1403,6 +1404,10 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
if (MO.getReg() == ARM::CPSR)
return false;
}
+
+ if (I == B)
+ // The 'and' is below the comparison instruction.
+ return false;
}
// Set the "zero" bit in CPSR.