diff options
author | Dan Gohman <gohman@apple.com> | 2009-03-05 21:29:28 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-03-05 21:29:28 +0000 |
commit | 51bb47480ea510ffc490c603244995e8977bc379 (patch) | |
tree | 214869a4b08f26c8722bd5c864a39528ff336b9a | |
parent | 4bfcf2a2a64785f3f0f0dd8fa6f4052d6cd7c08c (diff) |
When creating X86ISD::INC and X86ISD::DEC nodes, only add one operand.
The extra operand didn't appear to cause any trouble, but it was
erroneous regardless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66206 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 33eee7a736..9ce5e484e7 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5370,6 +5370,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, SelectionDAG &DAG) { // doing a separate TEST. if (Op.getResNo() == 0) { unsigned Opcode = 0; + unsigned NumOperands = 0; switch (Op.getNode()->getOpcode()) { case ISD::ADD: // Due to an isel shortcoming, be conservative if this add is likely to @@ -5387,16 +5388,19 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, SelectionDAG &DAG) { // An add of one will be selected as an INC. if (C->getAPIntValue() == 1) { Opcode = X86ISD::INC; + NumOperands = 1; break; } // An add of negative one (subtract of one) will be selected as a DEC. if (C->getAPIntValue().isAllOnesValue()) { Opcode = X86ISD::DEC; + NumOperands = 1; break; } } // Otherwise use a regular EFLAGS-setting add. Opcode = X86ISD::ADD; + NumOperands = 2; break; case ISD::SUB: // Due to the ISEL shortcoming noted above, be conservative if this sub is @@ -5407,6 +5411,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, SelectionDAG &DAG) { goto default_case; // Otherwise use a regular EFLAGS-setting sub. Opcode = X86ISD::SUB; + NumOperands = 2; break; case X86ISD::ADD: case X86ISD::SUB: @@ -5420,7 +5425,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, SelectionDAG &DAG) { if (Opcode != 0) { const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::i32); SmallVector<SDValue, 4> Ops; - for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) + for (unsigned i = 0, e = NumOperands; i != e; ++i) Ops.push_back(Op.getOperand(i)); SDValue New = DAG.getNode(Opcode, dl, VTs, 2, &Ops[0], Ops.size()); DAG.ReplaceAllUsesWith(Op, New); |