aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChris Lattner <sabre@nondot.org>2006-09-28 06:01:17 +0000
committerChris Lattner <sabre@nondot.org>2006-09-28 06:01:17 +0000
commitf308ea01d5e805ec07f479a79c753fa04541ec96 (patch)
tree4a0cd1d6fb34bf4c7cc669a4bc05df3830efceaf
parentf6e70fa0d339f86b2cce54afbc66f1b141ae71da (diff)
add a note about a general improvement to the code generator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30642 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/README.txt16
1 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/README.txt b/lib/Target/README.txt
index 48298fae87..e77573e007 100644
--- a/lib/Target/README.txt
+++ b/lib/Target/README.txt
@@ -1,6 +1,20 @@
Target Independent Opportunities:
-===-------------------------------------------------------------------------===
+//===---------------------------------------------------------------------===//
+
+We should make the following changes to clean up MachineInstr:
+
+1. Add an Opcode field to TargetInstrDescriptor, so you can tell the opcode of
+ an instruction with just a TargetInstrDescriptor*.
+2. Remove the Opcode field from MachineInstr, replacing it with a
+ TargetInstrDescriptor*.
+3. Getting information about a machine instr then becomes:
+ MI->getInfo()->isTwoAddress()
+ instead of:
+ const TargetInstrInfo &TII = ...
+ TII.isTwoAddrInstr(MI->getOpcode())
+
+//===---------------------------------------------------------------------===//
FreeBench/mason contains code like this: