diff options
author | Chris Lattner <sabre@nondot.org> | 2008-02-17 21:03:36 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2008-02-17 21:03:36 +0000 |
commit | dd12f96c5e2292e398f363cf352d6a95847a8a55 (patch) | |
tree | b2e7359673f3e5d22968e0882371f02ef0877180 | |
parent | 5329bb22e9b6374d62919981c1ef8775b42945eb (diff) |
Fold (-x + -y) -> -(x+y) which promotes better association, fixing
the second half of PR2047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47244 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Transforms/Scalar/InstructionCombining.cpp | 12 | ||||
-rw-r--r-- | test/Transforms/InstCombine/addnegneg.ll | 12 |
2 files changed, 22 insertions, 2 deletions
diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp index c9ff01b907..1ecefeb82b 100644 --- a/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/lib/Transforms/Scalar/InstructionCombining.cpp @@ -2090,8 +2090,16 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) { } // -A + B --> B - A - if (Value *V = dyn_castNegVal(LHS)) - return BinaryOperator::createSub(RHS, V); + // -A + -B --> -(A + B) + if (Value *LHSV = dyn_castNegVal(LHS)) { + if (Value *RHSV = dyn_castNegVal(RHS)) { + Instruction *NewAdd = BinaryOperator::createAdd(LHSV, RHSV, "sum"); + InsertNewInstBefore(NewAdd, I); + return BinaryOperator::createNeg(NewAdd); + } + + return BinaryOperator::createSub(RHS, LHSV); + } // A + -B --> A - B if (!isa<Constant>(RHS)) diff --git a/test/Transforms/InstCombine/addnegneg.ll b/test/Transforms/InstCombine/addnegneg.ll new file mode 100644 index 0000000000..f3b9565a51 --- /dev/null +++ b/test/Transforms/InstCombine/addnegneg.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep { sub } | count 1 +; PR2047 + +define i32 @l(i32 %a, i32 %b, i32 %c, i32 %d) { +entry: + %b.neg = sub i32 0, %b ; <i32> [#uses=1] + %c.neg = sub i32 0, %c ; <i32> [#uses=1] + %sub4 = add i32 %c.neg, %b.neg ; <i32> [#uses=1] + %sub6 = add i32 %sub4, %d ; <i32> [#uses=1] + ret i32 %sub6 +} + |