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| author | Chris Lattner <sabre@nondot.org> | 2008-07-10 23:46:13 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-07-10 23:46:13 +0000 |
| commit | c563e1d8fe2e0e9bb47e99ec55c277404969287e (patch) | |
| tree | 38a772923671afd97a08c5c82b1d2701a17e8c70 | |
| parent | 70587ea813986bb0dbef71610091d496e28c22a6 (diff) | |
Fix a bug in the soft-float handling of FCOPYSIGN that Duncan noticed
when working on legalizetypes. Both legalizetypes and legalizeops now
produce hte same code for CodeGen/ARM/fcopysign.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53435 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 80502cfe69..4b4c02bd8d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -547,8 +547,11 @@ SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); - } else if (SizeDiff < 0) - SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); + } else if (SizeDiff < 0) { + SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); + SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, + DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); + } // Clear the sign bit of first operand. SDOperand Mask2 = (VT == MVT::f64) |