diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-02-21 19:30:30 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-02-21 19:30:30 +0000 |
| commit | beb07e117db43bdd9f241a9f3b086ac62c6a01ce (patch) | |
| tree | a338b5b41ab374a8600cf3ec837914dc10de99f9 | |
| parent | bf156d1ae6ce469cc5cd0c9dcb94802982f8958d (diff) | |
A big more cleaning up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26302 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 37 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 4 |
2 files changed, 18 insertions, 23 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 4ea5afd59e..d5fbd9cc15 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2367,31 +2367,12 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB; //===----------------------------------------------------------------------===// -// Floating Point Stack Support -//===----------------------------------------------------------------------===// - -include "X86InstrFPStack.td" - -//===----------------------------------------------------------------------===// -// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) -//===----------------------------------------------------------------------===// - -include "X86InstrMMX.td" - -//===----------------------------------------------------------------------===// -// XMM Packed Floating point support (requires SSE / SSE2) -//===----------------------------------------------------------------------===// - -include "X86InstrSSE.td" - -//===----------------------------------------------------------------------===// // Miscellaneous Instructions //===----------------------------------------------------------------------===// def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>, TB, Imp<[],[EAX,EDX]>; - //===----------------------------------------------------------------------===// // Alias Instructions //===----------------------------------------------------------------------===// @@ -2409,6 +2390,24 @@ def MOV32r0 : I<0x31, MRMInitReg, (ops R32:$dst), [(set R32:$dst, 0)]>; //===----------------------------------------------------------------------===// +// Floating Point Stack Support +//===----------------------------------------------------------------------===// + +include "X86InstrFPStack.td" + +//===----------------------------------------------------------------------===// +// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2) +//===----------------------------------------------------------------------===// + +include "X86InstrMMX.td" + +//===----------------------------------------------------------------------===// +// XMM Floating point support (requires SSE / SSE2) +//===----------------------------------------------------------------------===// + +include "X86InstrSSE.td" + +//===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index d529206486..722cfba071 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -100,10 +100,6 @@ def ANDNPDrm : I<0x55, MRMSrcMem, (ops V2F64:$dst, V2F64:$src1, f128mem:$src2), Requires<[HasSSE2]>, TB, OpSize; } -//===----------------------------------------------------------------------===// -// XMM Floating point support (requires SSE / SSE2) -//===----------------------------------------------------------------------===// - def MOVSSrr : I<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src), "movss {$src, $dst|$dst, $src}", []>, Requires<[HasSSE1]>, XS; |