diff options
| author | Chris Lattner <sabre@nondot.org> | 2004-05-09 23:16:33 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-05-09 23:16:33 +0000 |
| commit | 9984fd0df9f4a07345c46ade9d8d7d5a4829a967 (patch) | |
| tree | 18d85f22ca9d2b0684641ac8d213f1c32e3d3fc4 | |
| parent | 96e3b426d5cab4a7ea4bb3c51facf7bb5362e0e5 (diff) | |
Fix some comments, avoid sign extending booleans when zero extend works fine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13440 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelSimple.cpp | 10 |
2 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 62002e7dc7..38503886de 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -886,9 +886,9 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, // each, then uses a conditional move to handle the overflow case. For // example, a setlt for long would generate code like this: // - // AL = lo(op1) < lo(op2) // Signedness depends on operands - // BL = hi(op1) < hi(op2) // Always unsigned comparison - // dest = hi(op1) == hi(op2) ? AL : BL; + // AL = lo(op1) < lo(op2) // Always unsigned comparison + // BL = hi(op1) < hi(op2) // Signedness depends on operands + // dest = hi(op1) == hi(op2) ? BL : AL; // // FIXME: This would be much better if we had hierarchical register @@ -960,7 +960,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, // // AL = lo(op1) < lo(op2) // Signedness depends on operands // BL = hi(op1) < hi(op2) // Always unsigned comparison - // dest = hi(op1) == hi(op2) ? AL : BL; + // dest = hi(op1) == hi(op2) ? BL : AL; // // FIXME: This would be much better if we had hierarchical register @@ -1193,7 +1193,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB, /// operand, in the specified target register. /// void ISel::promote32(unsigned targetReg, const ValueRecord &VR) { - bool isUnsigned = VR.Ty->isUnsigned(); + bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy; Value *Val = VR.Val; const Type *Ty = VR.Ty; diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 62002e7dc7..38503886de 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -886,9 +886,9 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, // each, then uses a conditional move to handle the overflow case. For // example, a setlt for long would generate code like this: // - // AL = lo(op1) < lo(op2) // Signedness depends on operands - // BL = hi(op1) < hi(op2) // Always unsigned comparison - // dest = hi(op1) == hi(op2) ? AL : BL; + // AL = lo(op1) < lo(op2) // Always unsigned comparison + // BL = hi(op1) < hi(op2) // Signedness depends on operands + // dest = hi(op1) == hi(op2) ? BL : AL; // // FIXME: This would be much better if we had hierarchical register @@ -960,7 +960,7 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, // // AL = lo(op1) < lo(op2) // Signedness depends on operands // BL = hi(op1) < hi(op2) // Always unsigned comparison - // dest = hi(op1) == hi(op2) ? AL : BL; + // dest = hi(op1) == hi(op2) ? BL : AL; // // FIXME: This would be much better if we had hierarchical register @@ -1193,7 +1193,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB, /// operand, in the specified target register. /// void ISel::promote32(unsigned targetReg, const ValueRecord &VR) { - bool isUnsigned = VR.Ty->isUnsigned(); + bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy; Value *Val = VR.Val; const Type *Ty = VR.Ty; |