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| author | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-03-20 16:46:44 +0000 |
|---|---|---|
| committer | Lauro Ramos Venancio <lauro.venancio@gmail.com> | 2007-03-20 16:46:44 +0000 |
| commit | 8334b9fa3bdfca1cc3c85b4156b165ed3f5f8c99 (patch) | |
| tree | 13fda99f4c81265889189a57fae4f64830b8323d | |
| parent | 3a7f7ab73f43c5a17867071eab335b07787c779a (diff) | |
CopyToReg source operand can be a physical register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35213 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index ca256deeaf..10a85868d5 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -475,9 +475,25 @@ void ScheduleDAG::EmitNode(SDNode *Node, else InReg = getVR(Node->getOperand(2), VRBaseMap); unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); - if (InReg != DestReg) // Coalesced away the copy? - MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, - RegMap->getRegClass(InReg)); + if (InReg != DestReg) {// Coalesced away the copy? + const TargetRegisterClass *TRC = 0; + // Get the target register class + if (MRegisterInfo::isVirtualRegister(InReg)) { + TRC = RegMap->getRegClass(InReg); + } else { + // Pick the register class of the right type that contains this + // physreg. + for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(), + E = MRI->regclass_end(); I != E; ++I) + if ((*I)->hasType(Node->getOperand(2).getValueType()) && + (*I)->contains(InReg)) { + TRC = *I; + break; + } + assert(TRC && "Couldn't find register class for reg copy!"); + } + MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC); + } break; } case ISD::CopyFromReg: { |