diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-10-11 21:06:01 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-10-11 21:06:01 +0000 |
| commit | 82a9164fb4b86164b642d76584a6efdc8bafccca (patch) | |
| tree | d17d9e901c885b2f51ef95311ed3d697d1dba154 | |
| parent | af9db75943c11eebd642c1645d3c3f4003fe37e3 (diff) | |
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30892 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 17 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 6 |
2 files changed, 14 insertions, 9 deletions
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index a74116f1b2..76aa0da2b3 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -148,7 +148,8 @@ namespace { bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale, SDOperand &Index, SDOperand &Disp); bool SelectScalarSSELoad(SDOperand N, SDOperand &Base, SDOperand &Scale, - SDOperand &Index, SDOperand &Disp); + SDOperand &Index, SDOperand &Disp, + SDOperand &InChain, SDOperand &OutChain); bool TryFoldLoad(SDOperand P, SDOperand N, SDOperand &Base, SDOperand &Scale, SDOperand &Index, SDOperand &Disp); @@ -781,20 +782,22 @@ bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale, /// match a load whose top elements are either undef or zeros. The load flavor /// is derived from the type of N, which is either v4f32 or v2f64. bool X86DAGToDAGISel::SelectScalarSSELoad(SDOperand N, SDOperand &Base, - SDOperand &Scale, - SDOperand &Index, SDOperand &Disp) { -#if 0 + SDOperand &Scale, SDOperand &Index, + SDOperand &Disp, SDOperand &InChain, + SDOperand &OutChain) { if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { - if (N.getOperand(0).getOpcode() == ISD::LOAD) { - SDOperand LoadAddr = N.getOperand(0).getOperand(0); + InChain = N.getOperand(0); + if (ISD::isNON_EXTLoad(InChain.Val)) { + LoadSDNode *LD = cast<LoadSDNode>(InChain); + SDOperand LoadAddr = LD->getBasePtr(); if (!SelectAddr(LoadAddr, Base, Scale, Index, Disp)) return false; + OutChain = LD->getChain(); return true; } } // TODO: Also handle the case where we explicitly require zeros in the top // elements. This is a vector shuffle from the zero vector. -#endif return false; } diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 81f59fb491..43965dda79 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -39,8 +39,10 @@ def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>; // These are 'extloads' from a scalar to the low element of a vector, zeroing // the top elements. These are used for the SSE 'ss' and 'sd' instruction // forms. -def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", []>; -def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", []>; +def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [], + [SDNPHasChain]>; +def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [], + [SDNPHasChain]>; def ssmem : Operand<v4f32> { let PrintMethod = "printf32mem"; |