diff options
| author | Chris Lattner <sabre@nondot.org> | 2007-03-02 05:12:29 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2007-03-02 05:12:29 +0000 |
| commit | 82932a5e4a2911cd5faa6376fa9d5dfac9e52091 (patch) | |
| tree | e132c5817a45b20b886f4c5e5adeeb02e3c3099f | |
| parent | 9b6f57c303c2aa2e2509fd663216e4e53edd9dc4 (diff) | |
argument lowering should copy from the vreg shadows of live-in arguments
passed in registers, not directly from the pregs themselves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34838 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 65593ebb9b..2fb89c3282 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -627,8 +627,8 @@ SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG, RC = X86::VR128RegisterClass; } - SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); - AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the @@ -877,8 +877,8 @@ X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) { RC = X86::VR128RegisterClass; } - SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); - AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the @@ -1116,9 +1116,9 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) { assert(MVT::isVector(RegVT)); RC = X86::VR128RegisterClass; } - - SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT); - AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + + unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); + SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT); // If this is an 8 or 16-bit value, it is really passed promoted to 32 // bits. Insert an assert[sz]ext to capture this, then truncate to the |