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| author | Evan Cheng <evan.cheng@apple.com> | 2007-09-04 20:20:29 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-09-04 20:20:29 +0000 |
| commit | 67c906dce729d64861af8ca708f5e19d6a058b35 (patch) | |
| tree | 38be9b8cc6dbcba20b19b37b91717a30ceaf7e1d | |
| parent | 425e8c7eaee57e3c9dab6701bf2ae6872beab628 (diff) | |
Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41711 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 10 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/rotl-64.ll | 20 |
2 files changed, 30 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 5f92c4f0d3..f55ce6cacb 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -338,6 +338,10 @@ def RLDIMI : MDForm_1<30, 3, } // Rotate instructions. +def RLDCL : MDForm_1<30, 0, + (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), + "rldcl $rA, $rS, $rB, $MB", IntRotateD, + []>, isPPC64; def RLDICL : MDForm_1<30, 0, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), "rldicl $rA, $rS, $SH, $MB", IntRotateD, @@ -579,6 +583,12 @@ def : Pat<(shl G8RC:$in, (i32 imm:$imm)), def : Pat<(srl G8RC:$in, (i32 imm:$imm)), (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; +// ROTL +def : Pat<(rotl G8RC:$in, GPRC:$sh), + (RLDCL G8RC:$in, GPRC:$sh, 0)>; +def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), + (RLDICL G8RC:$in, imm:$imm, 0)>; + // Hi and Lo for Darwin Global Addresses. def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; diff --git a/test/CodeGen/PowerPC/rotl-64.ll b/test/CodeGen/PowerPC/rotl-64.ll new file mode 100644 index 0000000000..3963d9a9d7 --- /dev/null +++ b/test/CodeGen/PowerPC/rotl-64.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep rldicl +; RUN: llvm-as < %s | llc -march=ppc64 | grep rldcl +; PR1613 + +define i64 @t1(i64 %A) { + %tmp1 = lshr i64 %A, 57 + %tmp2 = shl i64 %A, 7 + %tmp3 = or i64 %tmp1, %tmp2 + ret i64 %tmp3 +} + +define i64 @t2(i64 %A, i8 zeroext %Amt) { + %Amt1 = zext i8 %Amt to i64 + %tmp1 = lshr i64 %A, %Amt1 + %Amt2 = sub i8 64, %Amt + %Amt3 = zext i8 %Amt2 to i64 + %tmp2 = shl i64 %A, %Amt3 + %tmp3 = or i64 %tmp1, %tmp2 + ret i64 %tmp3 +} |